1 /* $NetBSD: r600_reg.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __R600_REG_H__ 31 #define __R600_REG_H__ 32 33 #define R600_PCIE_PORT_INDEX 0x0038 34 #define R600_PCIE_PORT_DATA 0x003c 35 36 #define R600_RCU_INDEX 0x0100 37 #define R600_RCU_DATA 0x0104 38 39 #define R600_UVD_CTX_INDEX 0xf4a0 40 #define R600_UVD_CTX_DATA 0xf4a4 41 42 #define R600_MC_VM_FB_LOCATION 0x2180 43 #define R600_MC_FB_BASE_MASK 0x0000FFFF 44 #define R600_MC_FB_BASE_SHIFT 0 45 #define R600_MC_FB_TOP_MASK 0xFFFF0000 46 #define R600_MC_FB_TOP_SHIFT 16 47 #define R600_MC_VM_AGP_TOP 0x2184 48 #define R600_MC_AGP_TOP_MASK 0x0003FFFF 49 #define R600_MC_AGP_TOP_SHIFT 0 50 #define R600_MC_VM_AGP_BOT 0x2188 51 #define R600_MC_AGP_BOT_MASK 0x0003FFFF 52 #define R600_MC_AGP_BOT_SHIFT 0 53 #define R600_MC_VM_AGP_BASE 0x218c 54 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 55 #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 56 #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 57 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 58 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 59 60 #define R700_MC_VM_FB_LOCATION 0x2024 61 #define R700_MC_FB_BASE_MASK 0x0000FFFF 62 #define R700_MC_FB_BASE_SHIFT 0 63 #define R700_MC_FB_TOP_MASK 0xFFFF0000 64 #define R700_MC_FB_TOP_SHIFT 16 65 #define R700_MC_VM_AGP_TOP 0x2028 66 #define R700_MC_AGP_TOP_MASK 0x0003FFFF 67 #define R700_MC_AGP_TOP_SHIFT 0 68 #define R700_MC_VM_AGP_BOT 0x202c 69 #define R700_MC_AGP_BOT_MASK 0x0003FFFF 70 #define R700_MC_AGP_BOT_SHIFT 0 71 #define R700_MC_VM_AGP_BASE 0x2030 72 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 73 #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 74 #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 75 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 76 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 77 78 #define R600_RAMCFG 0x2408 79 # define R600_CHANSIZE (1 << 7) 80 # define R600_CHANSIZE_OVERRIDE (1 << 10) 81 82 83 #define R600_GENERAL_PWRMGT 0x618 84 # define R600_OPEN_DRAIN_PADS (1 << 11) 85 86 #define R600_LOWER_GPIO_ENABLE 0x710 87 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 88 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c 89 #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 90 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 91 92 #define R600_D1GRPH_SWAP_CONTROL 0x610C 93 # define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 94 # define R600_D1GRPH_SWAP_ENDIAN_NONE 0 95 # define R600_D1GRPH_SWAP_ENDIAN_16BIT 1 96 # define R600_D1GRPH_SWAP_ENDIAN_32BIT 2 97 # define R600_D1GRPH_SWAP_ENDIAN_64BIT 3 98 # define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 99 # define R600_D1GRPH_RED_SEL_R 0 100 # define R600_D1GRPH_RED_SEL_G 1 101 # define R600_D1GRPH_RED_SEL_B 2 102 # define R600_D1GRPH_RED_SEL_A 3 103 # define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 104 # define R600_D1GRPH_GREEN_SEL_G 0 105 # define R600_D1GRPH_GREEN_SEL_B 1 106 # define R600_D1GRPH_GREEN_SEL_A 2 107 # define R600_D1GRPH_GREEN_SEL_R 3 108 # define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 109 # define R600_D1GRPH_BLUE_SEL_B 0 110 # define R600_D1GRPH_BLUE_SEL_A 1 111 # define R600_D1GRPH_BLUE_SEL_R 2 112 # define R600_D1GRPH_BLUE_SEL_G 3 113 # define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 114 # define R600_D1GRPH_ALPHA_SEL_A 0 115 # define R600_D1GRPH_ALPHA_SEL_R 1 116 # define R600_D1GRPH_ALPHA_SEL_G 2 117 # define R600_D1GRPH_ALPHA_SEL_B 3 118 119 #define R600_HDP_NONSURFACE_BASE 0x2c04 120 121 #define R600_BUS_CNTL 0x5420 122 # define R600_BIOS_ROM_DIS (1 << 1) 123 #define R600_CONFIG_CNTL 0x5424 124 #define R600_CONFIG_MEMSIZE 0x5428 125 #define R600_CONFIG_F0_BASE 0x542C 126 #define R600_CONFIG_APER_SIZE 0x5430 127 128 #define R600_BIF_FB_EN 0x5490 129 #define R600_FB_READ_EN (1 << 0) 130 #define R600_FB_WRITE_EN (1 << 1) 131 132 #define R600_CITF_CNTL 0x200c 133 #define R600_BLACKOUT_MASK 0x00000003 134 135 #define R700_MC_CITF_CNTL 0x25c0 136 137 #define R600_ROM_CNTL 0x1600 138 # define R600_SCK_OVERWRITE (1 << 1) 139 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 140 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 141 142 #define R600_CG_SPLL_FUNC_CNTL 0x600 143 # define R600_SPLL_BYPASS_EN (1 << 3) 144 #define R600_CG_SPLL_STATUS 0x60c 145 # define R600_SPLL_CHG_STATUS (1 << 1) 146 147 #define R600_BIOS_0_SCRATCH 0x1724 148 #define R600_BIOS_1_SCRATCH 0x1728 149 #define R600_BIOS_2_SCRATCH 0x172c 150 #define R600_BIOS_3_SCRATCH 0x1730 151 #define R600_BIOS_4_SCRATCH 0x1734 152 #define R600_BIOS_5_SCRATCH 0x1738 153 #define R600_BIOS_6_SCRATCH 0x173c 154 #define R600_BIOS_7_SCRATCH 0x1740 155 156 /* Audio, these regs were reverse enginered, 157 * so the chance is high that the naming is wrong 158 * R6xx+ ??? */ 159 160 /* Audio clocks */ 161 #define R600_AUDIO_PLL1_MUL 0x0514 162 #define R600_AUDIO_PLL1_DIV 0x0518 163 #define R600_AUDIO_PLL2_MUL 0x0524 164 #define R600_AUDIO_PLL2_DIV 0x0528 165 #define R600_AUDIO_CLK_SRCSEL 0x0534 166 167 /* Audio general */ 168 #define R600_AUDIO_ENABLE 0x7300 169 #define R600_AUDIO_TIMING 0x7344 170 171 /* Audio params */ 172 #define R600_AUDIO_VENDOR_ID 0x7380 173 #define R600_AUDIO_REVISION_ID 0x7384 174 #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 175 #define R600_AUDIO_NID1_NODE_COUNT 0x738c 176 #define R600_AUDIO_NID1_TYPE 0x7390 177 #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 178 #define R600_AUDIO_SUPPORTED_CODEC 0x7398 179 #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c 180 #define R600_AUDIO_NID2_CAPS 0x73a0 181 #define R600_AUDIO_NID3_CAPS 0x73a4 182 #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 183 184 /* Audio conn list */ 185 #define R600_AUDIO_CONN_LIST_LEN 0x73ac 186 #define R600_AUDIO_CONN_LIST 0x73b0 187 188 /* Audio verbs */ 189 #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 190 #define R600_AUDIO_PLAYING 0x73c4 191 #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 192 #define R600_AUDIO_CONFIG_DEFAULT 0x73cc 193 #define R600_AUDIO_PIN_SENSE 0x73d0 194 #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 195 #define R600_AUDIO_STATUS_BITS 0x73d8 196 197 #define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400) 198 #define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400) 199 /* DCE3.2 second instance starts at 0x7800 */ 200 #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400) 201 #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400) 202 203 #endif 204
Indexes created Sat Sep 20 22:09:52 GMT 2025