| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 146 uint32_t DCLK;
186 unsigned long dclk; member in struct:pp_clock_engine_request
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| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_llc.c | 64 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6dl-eckelmann-ci4x10.dts | 50 dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_processpptables.c | 766 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK);
769 ps->uvd_clocks.DCLK = 0;
1110 uvd_table->entries[i].dclk = ((unsigned long)entry->ucDClkHigh << 16)
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| amdgpu_smu10_hwmgr.c | 799 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
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| amdgpu_smu7_hwmgr.c | 3171 power_state->uvd_clocks.DCLK = 0;
3264 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3412 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
4234 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
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| amdgpu_smu8_hwmgr.c | 530 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
1394 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local in function:smu8_read_sensor
1743 dclk = uvd_table->entries[uvd_index].dclk;
1744 *((uint32_t *)value) = dclk;
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| amdgpu_vega10_hwmgr.c | 1410 dep_mm_table->entries[i].dclk) {
1412 dep_mm_table->entries[i].dclk;
2014 "Failed to get DCLK clock settings from VBIOS!",
2076 dep_table->entries[i].dclk ==
3080 power_state->uvd_clocks.DCLK = 0;
3158 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
4742 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_arcturus_ppt.c | 144 CLK_MAP(DCLK, PPCLK_DCLK),
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| amdgpu_navi10_ppt.c | 144 CLK_MAP(DCLK, PPCLK_DCLK),
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| amdgpu_vega20_ppt.c | 160 CLK_MAP(DCLK, PPCLK_DCLK),
809 /* dclk */
815 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
820 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
2184 /* dclk */
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 3704 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
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