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      1 /*	$NetBSD: intel_llc.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $	*/
      2 
      3 /*
      4  * SPDX-License-Identifier: MIT
      5  *
      6  * Copyright  2019 Intel Corporation
      7  */
      8 
      9 #include <sys/cdefs.h>
     10 __KERNEL_RCSID(0, "$NetBSD: intel_llc.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
     11 
     12 #include <linux/cpufreq.h>
     13 
     14 #include "i915_drv.h"
     15 #include "intel_gt.h"
     16 #include "intel_llc.h"
     17 #include "intel_sideband.h"
     18 
     19 struct ia_constants {
     20 	unsigned int min_gpu_freq;
     21 	unsigned int max_gpu_freq;
     22 
     23 	unsigned int min_ring_freq;
     24 	unsigned int max_ia_freq;
     25 };
     26 
     27 static struct intel_gt *llc_to_gt(struct intel_llc *llc)
     28 {
     29 	return container_of(llc, struct intel_gt, llc);
     30 }
     31 
     32 static unsigned int cpu_max_MHz(void)
     33 {
     34 	struct cpufreq_policy *policy;
     35 	unsigned int max_khz;
     36 
     37 	policy = cpufreq_cpu_get(0);
     38 	if (policy) {
     39 		max_khz = policy->cpuinfo.max_freq;
     40 		cpufreq_cpu_put(policy);
     41 	} else {
     42 		/*
     43 		 * Default to measured freq if none found, PCU will ensure we
     44 		 * don't go over
     45 		 */
     46 		max_khz = tsc_khz;
     47 	}
     48 
     49 	return max_khz / 1000;
     50 }
     51 
     52 static bool get_ia_constants(struct intel_llc *llc,
     53 			     struct ia_constants *consts)
     54 {
     55 	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
     56 	struct intel_rps *rps = &llc_to_gt(llc)->rps;
     57 
     58 	if (rps->max_freq <= rps->min_freq)
     59 		return false;
     60 
     61 	consts->max_ia_freq = cpu_max_MHz();
     62 
     63 	consts->min_ring_freq =
     64 		intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
     65 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
     66 	consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
     67 
     68 	consts->min_gpu_freq = rps->min_freq;
     69 	consts->max_gpu_freq = rps->max_freq;
     70 	if (INTEL_GEN(i915) >= 9) {
     71 		/* Convert GT frequency to 50 HZ units */
     72 		consts->min_gpu_freq /= GEN9_FREQ_SCALER;
     73 		consts->max_gpu_freq /= GEN9_FREQ_SCALER;
     74 	}
     75 
     76 	return true;
     77 }
     78 
     79 static void calc_ia_freq(struct intel_llc *llc,
     80 			 unsigned int gpu_freq,
     81 			 const struct ia_constants *consts,
     82 			 unsigned int *out_ia_freq,
     83 			 unsigned int *out_ring_freq)
     84 {
     85 	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
     86 	const int diff = consts->max_gpu_freq - gpu_freq;
     87 	unsigned int ia_freq = 0, ring_freq = 0;
     88 
     89 	if (INTEL_GEN(i915) >= 9) {
     90 		/*
     91 		 * ring_freq = 2 * GT. ring_freq is in 100MHz units
     92 		 * No floor required for ring frequency on SKL.
     93 		 */
     94 		ring_freq = gpu_freq;
     95 	} else if (INTEL_GEN(i915) >= 8) {
     96 		/* max(2 * GT, DDR). NB: GT is 50MHz units */
     97 		ring_freq = max(consts->min_ring_freq, gpu_freq);
     98 	} else if (IS_HASWELL(i915)) {
     99 		ring_freq = mult_frac(gpu_freq, 5, 4);
    100 		ring_freq = max(consts->min_ring_freq, ring_freq);
    101 		/* leave ia_freq as the default, chosen by cpufreq */
    102 	} else {
    103 		const int min_freq = 15;
    104 		const int scale = 180;
    105 
    106 		/*
    107 		 * On older processors, there is no separate ring
    108 		 * clock domain, so in order to boost the bandwidth
    109 		 * of the ring, we need to upclock the CPU (ia_freq).
    110 		 *
    111 		 * For GPU frequencies less than 750MHz,
    112 		 * just use the lowest ring freq.
    113 		 */
    114 		if (gpu_freq < min_freq)
    115 			ia_freq = 800;
    116 		else
    117 			ia_freq = consts->max_ia_freq - diff * scale / 2;
    118 		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
    119 	}
    120 
    121 	*out_ia_freq = ia_freq;
    122 	*out_ring_freq = ring_freq;
    123 }
    124 
    125 static void gen6_update_ring_freq(struct intel_llc *llc)
    126 {
    127 	struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
    128 	struct ia_constants consts;
    129 	unsigned int gpu_freq;
    130 
    131 	if (!get_ia_constants(llc, &consts))
    132 		return;
    133 
    134 	/*
    135 	 * For each potential GPU frequency, load a ring frequency we'd like
    136 	 * to use for memory access.  We do this by specifying the IA frequency
    137 	 * the PCU should use as a reference to determine the ring frequency.
    138 	 */
    139 	for (gpu_freq = consts.max_gpu_freq;
    140 	     gpu_freq >= consts.min_gpu_freq;
    141 	     gpu_freq--) {
    142 		unsigned int ia_freq, ring_freq;
    143 
    144 		calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
    145 		sandybridge_pcode_write(i915,
    146 					GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
    147 					ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
    148 					ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
    149 					gpu_freq);
    150 	}
    151 }
    152 
    153 void intel_llc_enable(struct intel_llc *llc)
    154 {
    155 	if (HAS_LLC(llc_to_gt(llc)->i915))
    156 		gen6_update_ring_freq(llc);
    157 }
    158 
    159 void intel_llc_disable(struct intel_llc *llc)
    160 {
    161 	/* Currently there is no HW configuration to be done to disable. */
    162 }
    163 
    164 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
    165 #include "selftest_llc.c"
    166 #endif
    167