Searched refs:DISP_CC_MDSS_AHB_CLK (Results 1 - 25 of 35) sorted by relevance

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/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dqcom,sm6115-dispcc.h14 #define DISP_CC_MDSS_AHB_CLK 2 macro
H A Dqcom,sm6375-dispcc.h14 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-qcm2290.h13 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-sm6125.h12 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-sc7180.h13 #define DISP_CC_MDSS_AHB_CLK 2 macro
H A Dqcom,sm4450-dispcc.h13 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-sm6350.h14 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-sc7280.h13 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,dispcc-sdm845.h12 #define DISP_CC_MDSS_AHB_CLK 0 macro
H A Dqcom,dispcc-sm8250.h12 #define DISP_CC_MDSS_AHB_CLK 0 macro
H A Dqcom,dispcc-sm8350.h12 #define DISP_CC_MDSS_AHB_CLK 0 macro
H A Dqcom,dispcc-sm8150.h12 #define DISP_CC_MDSS_AHB_CLK 0 macro
H A Dqcom,sm8450-dispcc.h13 #define DISP_CC_MDSS_AHB_CLK 1 macro
H A Dqcom,sm8550-dispcc.h14 #define DISP_CC_MDSS_AHB_CLK 2 macro
H A Dqcom,sm8650-dispcc.h14 #define DISP_CC_MDSS_AHB_CLK 2 macro
H A Dqcom,x1e80100-dispcc.h14 #define DISP_CC_MDSS_AHB_CLK 2 macro
H A Dqcom,dispcc-sc8280xp.h17 #define DISP_CC_MDSS_AHB_CLK 5 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi1410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1438 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1509 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1563 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1583 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1636 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
H A Dsc8280xp.dtsi3310 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3328 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
4096 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4125 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4214 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4293 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4370 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4442 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4515 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4533 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
[all...]
H A Dsm6125.dtsi1232 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1258 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1331 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1399 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
H A Dsc8180x.dtsi2937 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2976 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3075 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3142 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3161 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3209 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3225 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3303 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3449 <&dispcc DISP_CC_MDSS_AHB_CLK>;
[all...]
H A Dsm8150.dtsi3786 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3810 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3886 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3969 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4043 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4062 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4117 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
H A Dsm8350.dtsi2752 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2778 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2863 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2946 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3045 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3125 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
H A Dsc7180.dtsi3173 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3203 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3212 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3279 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3351 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3371 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
H A Dqcm2290.dtsi1628 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1695 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1767 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

Completed in 32 milliseconds

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