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      1 /*	$NetBSD: qcom,dispcc-sm8150.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
      9 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
     10 
     11 /* DISP_CC clock registers */
     12 #define DISP_CC_MDSS_AHB_CLK			0
     13 #define DISP_CC_MDSS_AHB_CLK_SRC		1
     14 #define DISP_CC_MDSS_BYTE0_CLK			2
     15 #define DISP_CC_MDSS_BYTE0_CLK_SRC		3
     16 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		4
     17 #define DISP_CC_MDSS_BYTE0_INTF_CLK		5
     18 #define DISP_CC_MDSS_BYTE1_CLK			6
     19 #define DISP_CC_MDSS_BYTE1_CLK_SRC		7
     20 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC		8
     21 #define DISP_CC_MDSS_BYTE1_INTF_CLK		9
     22 #define DISP_CC_MDSS_DP_AUX1_CLK		10
     23 #define DISP_CC_MDSS_DP_AUX1_CLK_SRC		11
     24 #define DISP_CC_MDSS_DP_AUX_CLK			12
     25 #define DISP_CC_MDSS_DP_AUX_CLK_SRC		13
     26 #define DISP_CC_MDSS_DP_LINK1_CLK		14
     27 #define DISP_CC_MDSS_DP_LINK1_CLK_SRC		15
     28 #define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC	16
     29 #define DISP_CC_MDSS_DP_LINK1_INTF_CLK		17
     30 #define DISP_CC_MDSS_DP_LINK_CLK		18
     31 #define DISP_CC_MDSS_DP_LINK_CLK_SRC		19
     32 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC	20
     33 #define DISP_CC_MDSS_DP_LINK_INTF_CLK		21
     34 #define DISP_CC_MDSS_DP_PIXEL1_CLK		22
     35 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC		23
     36 #define DISP_CC_MDSS_DP_PIXEL2_CLK		24
     37 #define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC		25
     38 #define DISP_CC_MDSS_DP_PIXEL_CLK		26
     39 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC		27
     40 #define DISP_CC_MDSS_ESC0_CLK			28
     41 #define DISP_CC_MDSS_ESC0_CLK_SRC		29
     42 #define DISP_CC_MDSS_ESC1_CLK			30
     43 #define DISP_CC_MDSS_ESC1_CLK_SRC		31
     44 #define DISP_CC_MDSS_MDP_CLK			32
     45 #define DISP_CC_MDSS_MDP_CLK_SRC		33
     46 #define DISP_CC_MDSS_MDP_LUT_CLK		34
     47 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK		35
     48 #define DISP_CC_MDSS_PCLK0_CLK			36
     49 #define DISP_CC_MDSS_PCLK0_CLK_SRC		37
     50 #define DISP_CC_MDSS_PCLK1_CLK			38
     51 #define DISP_CC_MDSS_PCLK1_CLK_SRC		39
     52 #define DISP_CC_MDSS_ROT_CLK			40
     53 #define DISP_CC_MDSS_ROT_CLK_SRC		41
     54 #define DISP_CC_MDSS_RSCC_AHB_CLK		42
     55 #define DISP_CC_MDSS_RSCC_VSYNC_CLK		43
     56 #define DISP_CC_MDSS_VSYNC_CLK			44
     57 #define DISP_CC_MDSS_VSYNC_CLK_SRC		45
     58 #define DISP_CC_PLL0				46
     59 #define DISP_CC_PLL1				47
     60 #define DISP_CC_MDSS_EDP_AUX_CLK		48
     61 #define DISP_CC_MDSS_EDP_AUX_CLK_SRC		49
     62 #define DISP_CC_MDSS_EDP_GTC_CLK		50
     63 #define DISP_CC_MDSS_EDP_GTC_CLK_SRC		51
     64 #define DISP_CC_MDSS_EDP_LINK_CLK		52
     65 #define DISP_CC_MDSS_EDP_LINK_CLK_SRC		53
     66 #define DISP_CC_MDSS_EDP_LINK_INTF_CLK		54
     67 #define DISP_CC_MDSS_EDP_PIXEL_CLK		55
     68 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC		56
     69 
     70 /* DISP_CC Reset */
     71 #define DISP_CC_MDSS_CORE_BCR			0
     72 #define DISP_CC_MDSS_RSCC_BCR			1
     73 
     74 /* DISP_CC GDSCR */
     75 #define MDSS_GDSC				0
     76 
     77 #endif
     78