HomeSort by: relevance | last modified time | path
    Searched refs:DMA0_REGISTER_OFFSET (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni_dma.c 67 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
91 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
112 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
173 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
203 reg_offset = DMA0_REGISTER_OFFSET;
radeon_ni.c 877 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1139 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1776 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1857 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1859 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
radeon_si.c 1329 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
3289 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3809 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3891 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3893 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4058 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4060 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
5546 offset = DMA0_REGISTER_OFFSET;
5558 offset = DMA0_REGISTER_OFFSET;
5965 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE
    [all...]
nid.h 1303 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
sid.h 1814 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dma.c 37 DMA0_REGISTER_OFFSET,
602 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
604 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
607 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
609 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
661 offset = DMA0_REGISTER_OFFSET;
673 offset = DMA0_REGISTER_OFFSET;
si_enums.h 134 #define DMA0_REGISTER_OFFSET 0x000
amdgpu_si.c 990 {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
sid.h 1877 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
amdgpu_gfx_v6_0.c 1721 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

Completed in 37 milliseconds