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Searched refs:DMEM_CONTROL (Results 1 - 25 of 36) sorted by relevancy

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/src/external/gpl3/gdb/dist/sim/testsuite/bfin/
lmu_cplb_multiple0.S	160 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 169 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 184 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 193 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 208 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 217 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 232 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 241 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 256 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 265 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0) [all...]
lmu_cplb_multiple1.S	162 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 171 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 186 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 195 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 210 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 219 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 234 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 243 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 258 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 267 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0) [all...]
se_brtarget_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004 143 WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_stall_if2.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004 140 WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_popkill.S	`40 #ifndef DMEM_CONTROL 41 #define DMEM_CONTROL 0xFFE00004 144 WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0); 145 //WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_event_quad.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_kill.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_kill_01.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_oneins_zoff.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lb_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lc_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lt_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_cc_kill.S	`126 WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0);`
/src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
lmu_cplb_multiple0.S	160 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 169 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 184 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 193 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 208 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 217 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 232 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 241 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 256 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 265 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0) [all...]
lmu_cplb_multiple1.S	162 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 171 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 186 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 195 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 210 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 219 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 234 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 243 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0); 258 WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); 267 WR_MMR(DMEM_CONTROL, ENDM \| DMC_AB_CACHE, p0, r0) [all...]
se_brtarget_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004 143 WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_stall_if2.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004 140 WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_popkill.S	`40 #ifndef DMEM_CONTROL 41 #define DMEM_CONTROL 0xFFE00004 144 WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0); 145 //WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1`
se_event_quad.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_kill.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_kill_01.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_oneins_zoff.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lb_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lc_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`
se_loop_mv2lt_stall.S	`38 #ifndef DMEM_CONTROL 39 #define DMEM_CONTROL 0xFFE00004`

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