1 //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp 2 // Description: Multiple CPLB Hit exceptions 3 # mach: bfin 4 # sim: --environment operating 5 6 #include "test.h" 7 .include "testutils.inc" 8 start 9 10 include(selfcheck.inc) 11 include(std.inc) 12 include(mmrs.inc) 13 14 //------------------------------------- 15 16 // Test LMU/CPLB exceptions 17 18 // Basic outline: 19 // Set exception handler 20 // program CPLB Entries 21 // Enable CPLB in DMEM_CNTL 22 // perform access 23 // verify exception occurred 24 25 CHECK_INIT(p5, 0xEFFFFFFC); 26 27 //------------------------- 28 // Zero the CPLB Address and Data regs. 29 30 LD32(p0, DCPLB_ADDR0); 31 R0 = 0; 32 [ P0 ++ ] = R0; // 0 33 [ P0 ++ ] = R0; // 1 34 [ P0 ++ ] = R0; // 2 35 [ P0 ++ ] = R0; // 3 36 [ P0 ++ ] = R0; // 4 37 [ P0 ++ ] = R0; // 5 38 [ P0 ++ ] = R0; // 6 39 [ P0 ++ ] = R0; // 7 40 [ P0 ++ ] = R0; // 8 41 [ P0 ++ ] = R0; // 9 42 [ P0 ++ ] = R0; // 10 43 [ P0 ++ ] = R0; // 11 44 [ P0 ++ ] = R0; // 12 45 [ P0 ++ ] = R0; // 13 46 [ P0 ++ ] = R0; // 14 47 [ P0 ++ ] = R0; // 15 48 49 LD32(p0, DCPLB_DATA0); 50 [ P0 ++ ] = R0; // 0 51 [ P0 ++ ] = R0; // 1 52 [ P0 ++ ] = R0; // 2 53 [ P0 ++ ] = R0; // 3 54 [ P0 ++ ] = R0; // 4 55 [ P0 ++ ] = R0; // 5 56 [ P0 ++ ] = R0; // 6 57 [ P0 ++ ] = R0; // 7 58 [ P0 ++ ] = R0; // 8 59 [ P0 ++ ] = R0; // 9 60 [ P0 ++ ] = R0; // 10 61 [ P0 ++ ] = R0; // 11 62 [ P0 ++ ] = R0; // 12 63 [ P0 ++ ] = R0; // 13 64 [ P0 ++ ] = R0; // 14 65 [ P0 ++ ] = R0; // 15 66 67 // Now set the CPLB entries we will need 68 69 70 71 72 // Data area for the desired error 73 WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0); 74 WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0); 75 WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0); 76 WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0); 77 WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0); 78 WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0); 79 WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0); 80 WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0); 81 WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0); 82 WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0); 83 WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0); 84 WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0); 85 WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0); 86 WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0); 87 WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0); 88 89 // MMR space 90 WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); 91 WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0); 92 93 // setup interrupt controller with exception handler address 94 WR_MMR_LABEL(EVT3, handler, p0, r1); 95 WR_MMR_LABEL(EVT15, int_15, p0, r1); 96 WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); 97 WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); 98 CSYNC; 99 100 // go to user mode. and enable exceptions 101 LD32_LABEL(r0, User); 102 RETI = R0; 103 104 // But first raise interrupt 15 so we can do one test 105 // in supervisor mode. 106 RAISE 15; 107 NOP; 108 109 RTI; 110 111 // Nops to work around ICache bug 112 NOP;NOP;NOP;NOP;NOP; 113 NOP;NOP;NOP;NOP;NOP; 114 115 handler: 116 // generic protection exception handler 117 // Inputs: 118 // p2: addr of CPLB entry to be modified ( current test) 119 // 120 // Outputs: 121 // r4: SEQSTAT 122 // r5: DCPLB_FAULT_ADDR 123 // r6: DCPLB_STATUS 124 // r7: RETX (instruction addr where exception occurred) 125 126 127 R4 = SEQSTAT; // Get exception cause 128 R4 <<= 24; // Clear HWERRCAUSE + SFTRESET 129 R4 >>= 24; 130 131 // read data addr which caused exception 132 RD_MMR(DCPLB_FAULT_ADDR, p0, r5); 133 134 RD_MMR(DCPLB_STATUS, p0, r6); 135 136 R7 = RETX; // get address of excepting instruction 137 138 // disable the offending CPLB entries 139 R2 = 0; 140 [ P2 ] = R2; 141 142 CSYNC; 143 144 // return from exception and re-execute offending instruction 145 RTX; 146 147 // Nops to work around ICache bug 148 NOP;NOP;NOP;NOP;NOP; 149 NOP;NOP;NOP;NOP;NOP; 150 151 152 int_15: 153 // Interrupt 15 handler - test will run in supervisor mode 154 155 //------------------------------------------------------- 156 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 157 158 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 159 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 160 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 161 CSYNC; 162 163 LD32(i1, 0x10000000); 164 R1 = 0x41C6 (Z); 165 LD32(p2, DCPLB_DATA1); 166 167 X0_1: [ I1 ] = R1; // Exception should occur here 168 169 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 170 CSYNC; 171 WR_MMR(DCPLB_DATA0, 0, p0, r0); 172 173 // Now check that handler read correct values 174 CHECKREG(r4,0x27); // supv and EXCPT_PROT 175 CHECKREG(r5, 0x10000000); 176 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1)); 177 CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!) 178 179 //------------------------------------------------------- 180 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 181 182 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 183 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 184 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 185 CSYNC; 186 187 LD32(i1, 0x10000000); 188 R1 = 0x167E (Z); 189 LD32(p2, DCPLB_DATA2); 190 191 X0_2: [ I1 ] = R1; // Exception should occur here 192 193 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 194 CSYNC; 195 WR_MMR(DCPLB_DATA0, 0, p0, r0); 196 197 // Now check that handler read correct values 198 CHECKREG(r4,0x27); // supv and EXCPT_PROT 199 CHECKREG(r5, 0x10000000); 200 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2)); 201 CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!) 202 203 //------------------------------------------------------- 204 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 205 206 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 207 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 208 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 209 CSYNC; 210 211 LD32(i1, 0x10000000); 212 R1 = 0x2781 (Z); 213 LD32(p2, DCPLB_DATA3); 214 215 X0_3: [ I1 ] = R1; // Exception should occur here 216 217 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 218 CSYNC; 219 WR_MMR(DCPLB_DATA0, 0, p0, r0); 220 221 // Now check that handler read correct values 222 CHECKREG(r4,0x27); // supv and EXCPT_PROT 223 CHECKREG(r5, 0x10000000); 224 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3)); 225 CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!) 226 227 //------------------------------------------------------- 228 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 229 230 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 231 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 232 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 233 CSYNC; 234 235 LD32(i1, 0x10000000); 236 R1 = 0x446B (Z); 237 LD32(p2, DCPLB_DATA4); 238 239 X0_4: [ I1 ] = R1; // Exception should occur here 240 241 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 242 CSYNC; 243 WR_MMR(DCPLB_DATA0, 0, p0, r0); 244 245 // Now check that handler read correct values 246 CHECKREG(r4,0x27); // supv and EXCPT_PROT 247 CHECKREG(r5, 0x10000000); 248 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4)); 249 CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!) 250 251 //------------------------------------------------------- 252 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 253 254 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 255 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 256 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 257 CSYNC; 258 259 LD32(i1, 0x10000000); 260 R1 = 0x794B (Z); 261 LD32(p2, DCPLB_DATA5); 262 263 X0_5: [ I1 ] = R1; // Exception should occur here 264 265 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 266 CSYNC; 267 WR_MMR(DCPLB_DATA0, 0, p0, r0); 268 269 // Now check that handler read correct values 270 CHECKREG(r4,0x27); // supv and EXCPT_PROT 271 CHECKREG(r5, 0x10000000); 272 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5)); 273 CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!) 274 275 //------------------------------------------------------- 276 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 277 278 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 279 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 280 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 281 CSYNC; 282 283 LD32(i1, 0x10000000); 284 R1 = 0x15FB (Z); 285 LD32(p2, DCPLB_DATA6); 286 287 X0_6: [ I1 ] = R1; // Exception should occur here 288 289 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 290 CSYNC; 291 WR_MMR(DCPLB_DATA0, 0, p0, r0); 292 293 // Now check that handler read correct values 294 CHECKREG(r4,0x27); // supv and EXCPT_PROT 295 CHECKREG(r5, 0x10000000); 296 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6)); 297 CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!) 298 299 //------------------------------------------------------- 300 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 301 302 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 303 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 304 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 305 CSYNC; 306 307 LD32(i1, 0x10000000); 308 R1 = 0x59E2 (Z); 309 LD32(p2, DCPLB_DATA7); 310 311 X0_7: [ I1 ] = R1; // Exception should occur here 312 313 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 314 CSYNC; 315 WR_MMR(DCPLB_DATA0, 0, p0, r0); 316 317 // Now check that handler read correct values 318 CHECKREG(r4,0x27); // supv and EXCPT_PROT 319 CHECKREG(r5, 0x10000000); 320 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7)); 321 CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!) 322 323 //------------------------------------------------------- 324 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 325 326 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 327 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 328 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 329 CSYNC; 330 331 LD32(i1, 0x10000000); 332 R1 = 0x1CFB (Z); 333 LD32(p2, DCPLB_DATA8); 334 335 X0_8: [ I1 ] = R1; // Exception should occur here 336 337 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 338 CSYNC; 339 WR_MMR(DCPLB_DATA0, 0, p0, r0); 340 341 // Now check that handler read correct values 342 CHECKREG(r4,0x27); // supv and EXCPT_PROT 343 CHECKREG(r5, 0x10000000); 344 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8)); 345 CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!) 346 347 //------------------------------------------------------- 348 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 349 350 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 351 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 352 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 353 CSYNC; 354 355 LD32(i1, 0x10000000); 356 R1 = 0x3F54 (Z); 357 LD32(p2, DCPLB_DATA9); 358 359 X0_9: [ I1 ] = R1; // Exception should occur here 360 361 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 362 CSYNC; 363 WR_MMR(DCPLB_DATA0, 0, p0, r0); 364 365 // Now check that handler read correct values 366 CHECKREG(r4,0x27); // supv and EXCPT_PROT 367 CHECKREG(r5, 0x10000000); 368 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9)); 369 CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!) 370 371 //------------------------------------------------------- 372 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 373 374 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 375 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 376 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 377 CSYNC; 378 379 LD32(i1, 0x10000000); 380 R1 = 0x0FF6 (Z); 381 LD32(p2, DCPLB_DATA10); 382 383 X0_10: [ I1 ] = R1; // Exception should occur here 384 385 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 386 CSYNC; 387 WR_MMR(DCPLB_DATA0, 0, p0, r0); 388 389 // Now check that handler read correct values 390 CHECKREG(r4,0x27); // supv and EXCPT_PROT 391 CHECKREG(r5, 0x10000000); 392 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10)); 393 CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!) 394 395 //------------------------------------------------------- 396 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 397 398 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 399 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 400 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 401 CSYNC; 402 403 LD32(i1, 0x10000000); 404 R1 = 0x0ABD (Z); 405 LD32(p2, DCPLB_DATA11); 406 407 X0_11: [ I1 ] = R1; // Exception should occur here 408 409 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 410 CSYNC; 411 WR_MMR(DCPLB_DATA0, 0, p0, r0); 412 413 // Now check that handler read correct values 414 CHECKREG(r4,0x27); // supv and EXCPT_PROT 415 CHECKREG(r5, 0x10000000); 416 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11)); 417 CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!) 418 419 //------------------------------------------------------- 420 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 421 422 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 423 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 424 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 425 CSYNC; 426 427 LD32(i1, 0x10000000); 428 R1 = 0x31DF (Z); 429 LD32(p2, DCPLB_DATA12); 430 431 X0_12: [ I1 ] = R1; // Exception should occur here 432 433 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 434 CSYNC; 435 WR_MMR(DCPLB_DATA0, 0, p0, r0); 436 437 // Now check that handler read correct values 438 CHECKREG(r4,0x27); // supv and EXCPT_PROT 439 CHECKREG(r5, 0x10000000); 440 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12)); 441 CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!) 442 443 //------------------------------------------------------- 444 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 445 446 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 447 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 448 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 449 CSYNC; 450 451 LD32(i1, 0x10000000); 452 R1 = 0x237C (Z); 453 LD32(p2, DCPLB_DATA13); 454 455 X0_13: [ I1 ] = R1; // Exception should occur here 456 457 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 458 CSYNC; 459 WR_MMR(DCPLB_DATA0, 0, p0, r0); 460 461 // Now check that handler read correct values 462 CHECKREG(r4,0x27); // supv and EXCPT_PROT 463 CHECKREG(r5, 0x10000000); 464 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13)); 465 CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!) 466 467 //------------------------------------------------------- 468 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 469 470 WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 471 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 472 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 473 CSYNC; 474 475 LD32(i1, 0x10000000); 476 R1 = 0x2F1C (Z); 477 LD32(p2, DCPLB_DATA14); 478 479 X0_14: [ I1 ] = R1; // Exception should occur here 480 481 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 482 CSYNC; 483 WR_MMR(DCPLB_DATA0, 0, p0, r0); 484 485 // Now check that handler read correct values 486 CHECKREG(r4,0x27); // supv and EXCPT_PROT 487 CHECKREG(r5, 0x10000000); 488 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14)); 489 CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!) 490 491 //------------------------------------------------------- 492 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 493 494 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 495 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 496 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 497 CSYNC; 498 499 LD32(i1, 0x10000000); 500 R1 = 0x7DE1 (Z); 501 LD32(p2, DCPLB_DATA2); 502 503 X1_2: [ I1 ] = R1; // Exception should occur here 504 505 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 506 CSYNC; 507 WR_MMR(DCPLB_DATA1, 0, p0, r0); 508 509 // Now check that handler read correct values 510 CHECKREG(r4,0x27); // supv and EXCPT_PROT 511 CHECKREG(r5, 0x10000000); 512 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2)); 513 CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!) 514 515 //------------------------------------------------------- 516 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 517 518 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 519 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 520 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 521 CSYNC; 522 523 LD32(i1, 0x10000000); 524 R1 = 0x4487 (Z); 525 LD32(p2, DCPLB_DATA3); 526 527 X1_3: [ I1 ] = R1; // Exception should occur here 528 529 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 530 CSYNC; 531 WR_MMR(DCPLB_DATA1, 0, p0, r0); 532 533 // Now check that handler read correct values 534 CHECKREG(r4,0x27); // supv and EXCPT_PROT 535 CHECKREG(r5, 0x10000000); 536 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3)); 537 CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!) 538 539 //------------------------------------------------------- 540 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 541 542 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 543 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 544 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 545 CSYNC; 546 547 LD32(i1, 0x10000000); 548 R1 = 0x6201 (Z); 549 LD32(p2, DCPLB_DATA4); 550 551 X1_4: [ I1 ] = R1; // Exception should occur here 552 553 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 554 CSYNC; 555 WR_MMR(DCPLB_DATA1, 0, p0, r0); 556 557 // Now check that handler read correct values 558 CHECKREG(r4,0x27); // supv and EXCPT_PROT 559 CHECKREG(r5, 0x10000000); 560 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4)); 561 CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!) 562 563 //------------------------------------------------------- 564 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 565 566 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 567 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 568 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 569 CSYNC; 570 571 LD32(i1, 0x10000000); 572 R1 = 0x52BF (Z); 573 LD32(p2, DCPLB_DATA5); 574 575 X1_5: [ I1 ] = R1; // Exception should occur here 576 577 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 578 CSYNC; 579 WR_MMR(DCPLB_DATA1, 0, p0, r0); 580 581 // Now check that handler read correct values 582 CHECKREG(r4,0x27); // supv and EXCPT_PROT 583 CHECKREG(r5, 0x10000000); 584 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5)); 585 CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!) 586 587 //------------------------------------------------------- 588 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 589 590 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 591 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 592 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 593 CSYNC; 594 595 LD32(i1, 0x10000000); 596 R1 = 0x6231 (Z); 597 LD32(p2, DCPLB_DATA6); 598 599 X1_6: [ I1 ] = R1; // Exception should occur here 600 601 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 602 CSYNC; 603 WR_MMR(DCPLB_DATA1, 0, p0, r0); 604 605 // Now check that handler read correct values 606 CHECKREG(r4,0x27); // supv and EXCPT_PROT 607 CHECKREG(r5, 0x10000000); 608 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6)); 609 CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!) 610 611 //------------------------------------------------------- 612 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 613 614 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 615 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 616 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 617 CSYNC; 618 619 LD32(i1, 0x10000000); 620 R1 = 0x63DE (Z); 621 LD32(p2, DCPLB_DATA7); 622 623 X1_7: [ I1 ] = R1; // Exception should occur here 624 625 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 626 CSYNC; 627 WR_MMR(DCPLB_DATA1, 0, p0, r0); 628 629 // Now check that handler read correct values 630 CHECKREG(r4,0x27); // supv and EXCPT_PROT 631 CHECKREG(r5, 0x10000000); 632 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7)); 633 CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!) 634 635 //------------------------------------------------------- 636 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 637 638 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 639 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 640 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 641 CSYNC; 642 643 LD32(i1, 0x10000000); 644 R1 = 0x6956 (Z); 645 LD32(p2, DCPLB_DATA8); 646 647 X1_8: [ I1 ] = R1; // Exception should occur here 648 649 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 650 CSYNC; 651 WR_MMR(DCPLB_DATA1, 0, p0, r0); 652 653 // Now check that handler read correct values 654 CHECKREG(r4,0x27); // supv and EXCPT_PROT 655 CHECKREG(r5, 0x10000000); 656 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8)); 657 CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!) 658 659 //------------------------------------------------------- 660 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 661 662 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 663 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 664 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 665 CSYNC; 666 667 LD32(i1, 0x10000000); 668 R1 = 0x1372 (Z); 669 LD32(p2, DCPLB_DATA9); 670 671 X1_9: [ I1 ] = R1; // Exception should occur here 672 673 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 674 CSYNC; 675 WR_MMR(DCPLB_DATA1, 0, p0, r0); 676 677 // Now check that handler read correct values 678 CHECKREG(r4,0x27); // supv and EXCPT_PROT 679 CHECKREG(r5, 0x10000000); 680 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9)); 681 CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!) 682 683 //------------------------------------------------------- 684 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 685 686 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 687 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 688 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 689 CSYNC; 690 691 LD32(i1, 0x10000000); 692 R1 = 0x500F (Z); 693 LD32(p2, DCPLB_DATA10); 694 695 X1_10: [ I1 ] = R1; // Exception should occur here 696 697 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 698 CSYNC; 699 WR_MMR(DCPLB_DATA1, 0, p0, r0); 700 701 // Now check that handler read correct values 702 CHECKREG(r4,0x27); // supv and EXCPT_PROT 703 CHECKREG(r5, 0x10000000); 704 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10)); 705 CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!) 706 707 //------------------------------------------------------- 708 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 709 710 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 711 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 712 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 713 CSYNC; 714 715 LD32(i1, 0x10000000); 716 R1 = 0x2847 (Z); 717 LD32(p2, DCPLB_DATA11); 718 719 X1_11: [ I1 ] = R1; // Exception should occur here 720 721 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 722 CSYNC; 723 WR_MMR(DCPLB_DATA1, 0, p0, r0); 724 725 // Now check that handler read correct values 726 CHECKREG(r4,0x27); // supv and EXCPT_PROT 727 CHECKREG(r5, 0x10000000); 728 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11)); 729 CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!) 730 731 //------------------------------------------------------- 732 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 733 734 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 735 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 736 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 737 CSYNC; 738 739 LD32(i1, 0x10000000); 740 R1 = 0x2C67 (Z); 741 LD32(p2, DCPLB_DATA12); 742 743 X1_12: [ I1 ] = R1; // Exception should occur here 744 745 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 746 CSYNC; 747 WR_MMR(DCPLB_DATA1, 0, p0, r0); 748 749 // Now check that handler read correct values 750 CHECKREG(r4,0x27); // supv and EXCPT_PROT 751 CHECKREG(r5, 0x10000000); 752 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12)); 753 CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!) 754 755 //------------------------------------------------------- 756 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 757 758 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 759 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 760 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 761 CSYNC; 762 763 LD32(i1, 0x10000000); 764 R1 = 0x7566 (Z); 765 LD32(p2, DCPLB_DATA13); 766 767 X1_13: [ I1 ] = R1; // Exception should occur here 768 769 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 770 CSYNC; 771 WR_MMR(DCPLB_DATA1, 0, p0, r0); 772 773 // Now check that handler read correct values 774 CHECKREG(r4,0x27); // supv and EXCPT_PROT 775 CHECKREG(r5, 0x10000000); 776 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13)); 777 CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!) 778 779 //------------------------------------------------------- 780 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 781 782 WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 783 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 784 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 785 CSYNC; 786 787 LD32(i1, 0x10000000); 788 R1 = 0x4287 (Z); 789 LD32(p2, DCPLB_DATA14); 790 791 X1_14: [ I1 ] = R1; // Exception should occur here 792 793 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 794 CSYNC; 795 WR_MMR(DCPLB_DATA1, 0, p0, r0); 796 797 // Now check that handler read correct values 798 CHECKREG(r4,0x27); // supv and EXCPT_PROT 799 CHECKREG(r5, 0x10000000); 800 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14)); 801 CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!) 802 803 //------------------------------------------------------- 804 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 805 806 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 807 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 808 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 809 CSYNC; 810 811 LD32(i1, 0x10000000); 812 R1 = 0x3359 (Z); 813 LD32(p2, DCPLB_DATA3); 814 815 X2_3: [ I1 ] = R1; // Exception should occur here 816 817 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 818 CSYNC; 819 WR_MMR(DCPLB_DATA2, 0, p0, r0); 820 821 // Now check that handler read correct values 822 CHECKREG(r4,0x27); // supv and EXCPT_PROT 823 CHECKREG(r5, 0x10000000); 824 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3)); 825 CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!) 826 827 //------------------------------------------------------- 828 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 829 830 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 831 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 832 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 833 CSYNC; 834 835 LD32(i1, 0x10000000); 836 R1 = 0x4DAA (Z); 837 LD32(p2, DCPLB_DATA4); 838 839 X2_4: [ I1 ] = R1; // Exception should occur here 840 841 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 842 CSYNC; 843 WR_MMR(DCPLB_DATA2, 0, p0, r0); 844 845 // Now check that handler read correct values 846 CHECKREG(r4,0x27); // supv and EXCPT_PROT 847 CHECKREG(r5, 0x10000000); 848 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4)); 849 CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!) 850 851 //------------------------------------------------------- 852 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 853 854 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 855 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 856 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 857 CSYNC; 858 859 LD32(i1, 0x10000000); 860 R1 = 0x6488 (Z); 861 LD32(p2, DCPLB_DATA5); 862 863 X2_5: [ I1 ] = R1; // Exception should occur here 864 865 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 866 CSYNC; 867 WR_MMR(DCPLB_DATA2, 0, p0, r0); 868 869 // Now check that handler read correct values 870 CHECKREG(r4,0x27); // supv and EXCPT_PROT 871 CHECKREG(r5, 0x10000000); 872 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5)); 873 CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!) 874 875 //------------------------------------------------------- 876 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 877 878 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 879 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 880 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 881 CSYNC; 882 883 LD32(i1, 0x10000000); 884 R1 = 0x773C (Z); 885 LD32(p2, DCPLB_DATA6); 886 887 X2_6: [ I1 ] = R1; // Exception should occur here 888 889 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 890 CSYNC; 891 WR_MMR(DCPLB_DATA2, 0, p0, r0); 892 893 // Now check that handler read correct values 894 CHECKREG(r4,0x27); // supv and EXCPT_PROT 895 CHECKREG(r5, 0x10000000); 896 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6)); 897 CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!) 898 899 //------------------------------------------------------- 900 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 901 902 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 903 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 904 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 905 CSYNC; 906 907 LD32(i1, 0x10000000); 908 R1 = 0x6F59 (Z); 909 LD32(p2, DCPLB_DATA7); 910 911 X2_7: [ I1 ] = R1; // Exception should occur here 912 913 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 914 CSYNC; 915 WR_MMR(DCPLB_DATA2, 0, p0, r0); 916 917 // Now check that handler read correct values 918 CHECKREG(r4,0x27); // supv and EXCPT_PROT 919 CHECKREG(r5, 0x10000000); 920 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7)); 921 CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!) 922 923 //------------------------------------------------------- 924 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 925 926 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 927 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 928 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 929 CSYNC; 930 931 LD32(i1, 0x10000000); 932 R1 = 0x6EEA (Z); 933 LD32(p2, DCPLB_DATA8); 934 935 X2_8: [ I1 ] = R1; // Exception should occur here 936 937 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 938 CSYNC; 939 WR_MMR(DCPLB_DATA2, 0, p0, r0); 940 941 // Now check that handler read correct values 942 CHECKREG(r4,0x27); // supv and EXCPT_PROT 943 CHECKREG(r5, 0x10000000); 944 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8)); 945 CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!) 946 947 //------------------------------------------------------- 948 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 949 950 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 951 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 952 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 953 CSYNC; 954 955 LD32(i1, 0x10000000); 956 R1 = 0x5656 (Z); 957 LD32(p2, DCPLB_DATA9); 958 959 X2_9: [ I1 ] = R1; // Exception should occur here 960 961 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 962 CSYNC; 963 WR_MMR(DCPLB_DATA2, 0, p0, r0); 964 965 // Now check that handler read correct values 966 CHECKREG(r4,0x27); // supv and EXCPT_PROT 967 CHECKREG(r5, 0x10000000); 968 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9)); 969 CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!) 970 971 //------------------------------------------------------- 972 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 973 974 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 975 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 976 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 977 CSYNC; 978 979 LD32(i1, 0x10000000); 980 R1 = 0x6113 (Z); 981 LD32(p2, DCPLB_DATA10); 982 983 X2_10: [ I1 ] = R1; // Exception should occur here 984 985 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 986 CSYNC; 987 WR_MMR(DCPLB_DATA2, 0, p0, r0); 988 989 // Now check that handler read correct values 990 CHECKREG(r4,0x27); // supv and EXCPT_PROT 991 CHECKREG(r5, 0x10000000); 992 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10)); 993 CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!) 994 995 //------------------------------------------------------- 996 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 997 998 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 999 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1000 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1001 CSYNC; 1002 1003 LD32(i1, 0x10000000); 1004 R1 = 0x4A7B (Z); 1005 LD32(p2, DCPLB_DATA11); 1006 1007 X2_11: [ I1 ] = R1; // Exception should occur here 1008 1009 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1010 CSYNC; 1011 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1012 1013 // Now check that handler read correct values 1014 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1015 CHECKREG(r5, 0x10000000); 1016 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11)); 1017 CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!) 1018 1019 //------------------------------------------------------- 1020 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1021 1022 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1023 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1024 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1025 CSYNC; 1026 1027 LD32(i1, 0x10000000); 1028 R1 = 0x31D2 (Z); 1029 LD32(p2, DCPLB_DATA12); 1030 1031 X2_12: [ I1 ] = R1; // Exception should occur here 1032 1033 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1034 CSYNC; 1035 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1036 1037 // Now check that handler read correct values 1038 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1039 CHECKREG(r5, 0x10000000); 1040 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12)); 1041 CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!) 1042 1043 //------------------------------------------------------- 1044 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1045 1046 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1047 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1048 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1049 CSYNC; 1050 1051 LD32(i1, 0x10000000); 1052 R1 = 0x2D85 (Z); 1053 LD32(p2, DCPLB_DATA13); 1054 1055 X2_13: [ I1 ] = R1; // Exception should occur here 1056 1057 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1058 CSYNC; 1059 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1060 1061 // Now check that handler read correct values 1062 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1063 CHECKREG(r5, 0x10000000); 1064 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13)); 1065 CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!) 1066 1067 //------------------------------------------------------- 1068 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1069 1070 WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1071 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1072 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1073 CSYNC; 1074 1075 LD32(i1, 0x10000000); 1076 R1 = 0x19A1 (Z); 1077 LD32(p2, DCPLB_DATA14); 1078 1079 X2_14: [ I1 ] = R1; // Exception should occur here 1080 1081 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1082 CSYNC; 1083 WR_MMR(DCPLB_DATA2, 0, p0, r0); 1084 1085 // Now check that handler read correct values 1086 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1087 CHECKREG(r5, 0x10000000); 1088 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14)); 1089 CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!) 1090 1091 //------------------------------------------------------- 1092 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1093 1094 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1095 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1096 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1097 CSYNC; 1098 1099 LD32(i1, 0x10000000); 1100 R1 = 0x69D8 (Z); 1101 LD32(p2, DCPLB_DATA4); 1102 1103 X3_4: [ I1 ] = R1; // Exception should occur here 1104 1105 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1106 CSYNC; 1107 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1108 1109 // Now check that handler read correct values 1110 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1111 CHECKREG(r5, 0x10000000); 1112 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4)); 1113 CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!) 1114 1115 //------------------------------------------------------- 1116 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1117 1118 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1119 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1120 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1121 CSYNC; 1122 1123 LD32(i1, 0x10000000); 1124 R1 = 0x353C (Z); 1125 LD32(p2, DCPLB_DATA5); 1126 1127 X3_5: [ I1 ] = R1; // Exception should occur here 1128 1129 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1130 CSYNC; 1131 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1132 1133 // Now check that handler read correct values 1134 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1135 CHECKREG(r5, 0x10000000); 1136 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5)); 1137 CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!) 1138 1139 //------------------------------------------------------- 1140 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1141 1142 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1143 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1144 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1145 CSYNC; 1146 1147 LD32(i1, 0x10000000); 1148 R1 = 0x3B54 (Z); 1149 LD32(p2, DCPLB_DATA6); 1150 1151 X3_6: [ I1 ] = R1; // Exception should occur here 1152 1153 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1154 CSYNC; 1155 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1156 1157 // Now check that handler read correct values 1158 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1159 CHECKREG(r5, 0x10000000); 1160 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6)); 1161 CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!) 1162 1163 //------------------------------------------------------- 1164 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1165 1166 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1167 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1168 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1169 CSYNC; 1170 1171 LD32(i1, 0x10000000); 1172 R1 = 0x7D55 (Z); 1173 LD32(p2, DCPLB_DATA7); 1174 1175 X3_7: [ I1 ] = R1; // Exception should occur here 1176 1177 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1178 CSYNC; 1179 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1180 1181 // Now check that handler read correct values 1182 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1183 CHECKREG(r5, 0x10000000); 1184 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7)); 1185 CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!) 1186 1187 //------------------------------------------------------- 1188 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1189 1190 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1191 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1192 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1193 CSYNC; 1194 1195 LD32(i1, 0x10000000); 1196 R1 = 0x102F (Z); 1197 LD32(p2, DCPLB_DATA8); 1198 1199 X3_8: [ I1 ] = R1; // Exception should occur here 1200 1201 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1202 CSYNC; 1203 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1204 1205 // Now check that handler read correct values 1206 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1207 CHECKREG(r5, 0x10000000); 1208 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8)); 1209 CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!) 1210 1211 //------------------------------------------------------- 1212 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1213 1214 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1215 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1216 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1217 CSYNC; 1218 1219 LD32(i1, 0x10000000); 1220 R1 = 0x1B37 (Z); 1221 LD32(p2, DCPLB_DATA9); 1222 1223 X3_9: [ I1 ] = R1; // Exception should occur here 1224 1225 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1226 CSYNC; 1227 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1228 1229 // Now check that handler read correct values 1230 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1231 CHECKREG(r5, 0x10000000); 1232 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9)); 1233 CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!) 1234 1235 //------------------------------------------------------- 1236 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1237 1238 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1239 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1240 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1241 CSYNC; 1242 1243 LD32(i1, 0x10000000); 1244 R1 = 0x7AAE (Z); 1245 LD32(p2, DCPLB_DATA10); 1246 1247 X3_10: [ I1 ] = R1; // Exception should occur here 1248 1249 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1250 CSYNC; 1251 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1252 1253 // Now check that handler read correct values 1254 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1255 CHECKREG(r5, 0x10000000); 1256 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10)); 1257 CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!) 1258 1259 //------------------------------------------------------- 1260 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1261 1262 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1263 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1264 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1265 CSYNC; 1266 1267 LD32(i1, 0x10000000); 1268 R1 = 0x5E65 (Z); 1269 LD32(p2, DCPLB_DATA11); 1270 1271 X3_11: [ I1 ] = R1; // Exception should occur here 1272 1273 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1274 CSYNC; 1275 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1276 1277 // Now check that handler read correct values 1278 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1279 CHECKREG(r5, 0x10000000); 1280 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11)); 1281 CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!) 1282 1283 //------------------------------------------------------- 1284 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1285 1286 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1287 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1288 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1289 CSYNC; 1290 1291 LD32(i1, 0x10000000); 1292 R1 = 0x345B (Z); 1293 LD32(p2, DCPLB_DATA12); 1294 1295 X3_12: [ I1 ] = R1; // Exception should occur here 1296 1297 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1298 CSYNC; 1299 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1300 1301 // Now check that handler read correct values 1302 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1303 CHECKREG(r5, 0x10000000); 1304 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12)); 1305 CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!) 1306 1307 //------------------------------------------------------- 1308 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1309 1310 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1311 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1312 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1313 CSYNC; 1314 1315 LD32(i1, 0x10000000); 1316 R1 = 0x63DA (Z); 1317 LD32(p2, DCPLB_DATA13); 1318 1319 X3_13: [ I1 ] = R1; // Exception should occur here 1320 1321 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1322 CSYNC; 1323 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1324 1325 // Now check that handler read correct values 1326 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1327 CHECKREG(r5, 0x10000000); 1328 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13)); 1329 CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!) 1330 1331 //------------------------------------------------------- 1332 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1333 1334 WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1335 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1336 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1337 CSYNC; 1338 1339 LD32(i1, 0x10000000); 1340 R1 = 0x6102 (Z); 1341 LD32(p2, DCPLB_DATA14); 1342 1343 X3_14: [ I1 ] = R1; // Exception should occur here 1344 1345 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1346 CSYNC; 1347 WR_MMR(DCPLB_DATA3, 0, p0, r0); 1348 1349 // Now check that handler read correct values 1350 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1351 CHECKREG(r5, 0x10000000); 1352 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14)); 1353 CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!) 1354 1355 //------------------------------------------------------- 1356 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1357 1358 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1359 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1360 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1361 CSYNC; 1362 1363 LD32(i1, 0x10000000); 1364 R1 = 0x7A79 (Z); 1365 LD32(p2, DCPLB_DATA5); 1366 1367 X4_5: [ I1 ] = R1; // Exception should occur here 1368 1369 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1370 CSYNC; 1371 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1372 1373 // Now check that handler read correct values 1374 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1375 CHECKREG(r5, 0x10000000); 1376 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5)); 1377 CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!) 1378 1379 //------------------------------------------------------- 1380 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1381 1382 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1383 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1384 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1385 CSYNC; 1386 1387 LD32(i1, 0x10000000); 1388 R1 = 0x0398 (Z); 1389 LD32(p2, DCPLB_DATA6); 1390 1391 X4_6: [ I1 ] = R1; // Exception should occur here 1392 1393 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1394 CSYNC; 1395 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1396 1397 // Now check that handler read correct values 1398 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1399 CHECKREG(r5, 0x10000000); 1400 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6)); 1401 CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!) 1402 1403 //------------------------------------------------------- 1404 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1405 1406 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1407 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1408 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1409 CSYNC; 1410 1411 LD32(i1, 0x10000000); 1412 R1 = 0x28CC (Z); 1413 LD32(p2, DCPLB_DATA7); 1414 1415 X4_7: [ I1 ] = R1; // Exception should occur here 1416 1417 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1418 CSYNC; 1419 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1420 1421 // Now check that handler read correct values 1422 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1423 CHECKREG(r5, 0x10000000); 1424 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7)); 1425 CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!) 1426 1427 //------------------------------------------------------- 1428 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1429 1430 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1431 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1432 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1433 CSYNC; 1434 1435 LD32(i1, 0x10000000); 1436 R1 = 0x60E3 (Z); 1437 LD32(p2, DCPLB_DATA8); 1438 1439 X4_8: [ I1 ] = R1; // Exception should occur here 1440 1441 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1442 CSYNC; 1443 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1444 1445 // Now check that handler read correct values 1446 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1447 CHECKREG(r5, 0x10000000); 1448 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8)); 1449 CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!) 1450 1451 //------------------------------------------------------- 1452 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1453 1454 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1455 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1456 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1457 CSYNC; 1458 1459 LD32(i1, 0x10000000); 1460 R1 = 0x1F1A (Z); 1461 LD32(p2, DCPLB_DATA9); 1462 1463 X4_9: [ I1 ] = R1; // Exception should occur here 1464 1465 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1466 CSYNC; 1467 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1468 1469 // Now check that handler read correct values 1470 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1471 CHECKREG(r5, 0x10000000); 1472 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9)); 1473 CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!) 1474 1475 //------------------------------------------------------- 1476 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1477 1478 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1479 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1480 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1481 CSYNC; 1482 1483 LD32(i1, 0x10000000); 1484 R1 = 0x4B76 (Z); 1485 LD32(p2, DCPLB_DATA10); 1486 1487 X4_10: [ I1 ] = R1; // Exception should occur here 1488 1489 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1490 CSYNC; 1491 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1492 1493 // Now check that handler read correct values 1494 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1495 CHECKREG(r5, 0x10000000); 1496 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10)); 1497 CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!) 1498 1499 //------------------------------------------------------- 1500 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1501 1502 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1503 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1504 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1505 CSYNC; 1506 1507 LD32(i1, 0x10000000); 1508 R1 = 0x058E (Z); 1509 LD32(p2, DCPLB_DATA11); 1510 1511 X4_11: [ I1 ] = R1; // Exception should occur here 1512 1513 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1514 CSYNC; 1515 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1516 1517 // Now check that handler read correct values 1518 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1519 CHECKREG(r5, 0x10000000); 1520 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11)); 1521 CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!) 1522 1523 //------------------------------------------------------- 1524 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1525 1526 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1527 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1528 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1529 CSYNC; 1530 1531 LD32(i1, 0x10000000); 1532 R1 = 0x7A5F (Z); 1533 LD32(p2, DCPLB_DATA12); 1534 1535 X4_12: [ I1 ] = R1; // Exception should occur here 1536 1537 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1538 CSYNC; 1539 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1540 1541 // Now check that handler read correct values 1542 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1543 CHECKREG(r5, 0x10000000); 1544 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12)); 1545 CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!) 1546 1547 //------------------------------------------------------- 1548 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1549 1550 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1551 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1552 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1553 CSYNC; 1554 1555 LD32(i1, 0x10000000); 1556 R1 = 0x28D9 (Z); 1557 LD32(p2, DCPLB_DATA13); 1558 1559 X4_13: [ I1 ] = R1; // Exception should occur here 1560 1561 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1562 CSYNC; 1563 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1564 1565 // Now check that handler read correct values 1566 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1567 CHECKREG(r5, 0x10000000); 1568 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13)); 1569 CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!) 1570 1571 //------------------------------------------------------- 1572 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1573 1574 WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1575 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1576 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1577 CSYNC; 1578 1579 LD32(i1, 0x10000000); 1580 R1 = 0x0799 (Z); 1581 LD32(p2, DCPLB_DATA14); 1582 1583 X4_14: [ I1 ] = R1; // Exception should occur here 1584 1585 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1586 CSYNC; 1587 WR_MMR(DCPLB_DATA4, 0, p0, r0); 1588 1589 // Now check that handler read correct values 1590 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1591 CHECKREG(r5, 0x10000000); 1592 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14)); 1593 CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!) 1594 1595 //------------------------------------------------------- 1596 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1597 1598 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1599 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1600 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1601 CSYNC; 1602 1603 LD32(i1, 0x10000000); 1604 R1 = 0x388F (Z); 1605 LD32(p2, DCPLB_DATA6); 1606 1607 X5_6: [ I1 ] = R1; // Exception should occur here 1608 1609 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1610 CSYNC; 1611 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1612 1613 // Now check that handler read correct values 1614 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1615 CHECKREG(r5, 0x10000000); 1616 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6)); 1617 CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!) 1618 1619 //------------------------------------------------------- 1620 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1621 1622 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1623 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1624 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1625 CSYNC; 1626 1627 LD32(i1, 0x10000000); 1628 R1 = 0x751F (Z); 1629 LD32(p2, DCPLB_DATA7); 1630 1631 X5_7: [ I1 ] = R1; // Exception should occur here 1632 1633 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1634 CSYNC; 1635 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1636 1637 // Now check that handler read correct values 1638 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1639 CHECKREG(r5, 0x10000000); 1640 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7)); 1641 CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!) 1642 1643 //------------------------------------------------------- 1644 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1645 1646 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1647 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1648 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1649 CSYNC; 1650 1651 LD32(i1, 0x10000000); 1652 R1 = 0x493F (Z); 1653 LD32(p2, DCPLB_DATA8); 1654 1655 X5_8: [ I1 ] = R1; // Exception should occur here 1656 1657 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1658 CSYNC; 1659 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1660 1661 // Now check that handler read correct values 1662 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1663 CHECKREG(r5, 0x10000000); 1664 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8)); 1665 CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!) 1666 1667 //------------------------------------------------------- 1668 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1669 1670 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1671 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1672 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1673 CSYNC; 1674 1675 LD32(i1, 0x10000000); 1676 R1 = 0x0F36 (Z); 1677 LD32(p2, DCPLB_DATA9); 1678 1679 X5_9: [ I1 ] = R1; // Exception should occur here 1680 1681 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1682 CSYNC; 1683 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1684 1685 // Now check that handler read correct values 1686 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1687 CHECKREG(r5, 0x10000000); 1688 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9)); 1689 CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!) 1690 1691 //------------------------------------------------------- 1692 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1693 1694 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1695 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1696 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1697 CSYNC; 1698 1699 LD32(i1, 0x10000000); 1700 R1 = 0x48EE (Z); 1701 LD32(p2, DCPLB_DATA10); 1702 1703 X5_10: [ I1 ] = R1; // Exception should occur here 1704 1705 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1706 CSYNC; 1707 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1708 1709 // Now check that handler read correct values 1710 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1711 CHECKREG(r5, 0x10000000); 1712 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10)); 1713 CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!) 1714 1715 //------------------------------------------------------- 1716 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1717 1718 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1719 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1720 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1721 CSYNC; 1722 1723 LD32(i1, 0x10000000); 1724 R1 = 0x2043 (Z); 1725 LD32(p2, DCPLB_DATA11); 1726 1727 X5_11: [ I1 ] = R1; // Exception should occur here 1728 1729 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1730 CSYNC; 1731 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1732 1733 // Now check that handler read correct values 1734 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1735 CHECKREG(r5, 0x10000000); 1736 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11)); 1737 CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!) 1738 1739 //------------------------------------------------------- 1740 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1741 1742 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1743 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1744 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1745 CSYNC; 1746 1747 LD32(i1, 0x10000000); 1748 R1 = 0x3F78 (Z); 1749 LD32(p2, DCPLB_DATA12); 1750 1751 X5_12: [ I1 ] = R1; // Exception should occur here 1752 1753 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1754 CSYNC; 1755 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1756 1757 // Now check that handler read correct values 1758 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1759 CHECKREG(r5, 0x10000000); 1760 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12)); 1761 CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!) 1762 1763 //------------------------------------------------------- 1764 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1765 1766 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1767 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1768 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1769 CSYNC; 1770 1771 LD32(i1, 0x10000000); 1772 R1 = 0x1E4D (Z); 1773 LD32(p2, DCPLB_DATA13); 1774 1775 X5_13: [ I1 ] = R1; // Exception should occur here 1776 1777 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1778 CSYNC; 1779 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1780 1781 // Now check that handler read correct values 1782 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1783 CHECKREG(r5, 0x10000000); 1784 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13)); 1785 CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!) 1786 1787 //------------------------------------------------------- 1788 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1789 1790 WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1791 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1792 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1793 CSYNC; 1794 1795 LD32(i1, 0x10000000); 1796 R1 = 0x3D0D (Z); 1797 LD32(p2, DCPLB_DATA14); 1798 1799 X5_14: [ I1 ] = R1; // Exception should occur here 1800 1801 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1802 CSYNC; 1803 WR_MMR(DCPLB_DATA5, 0, p0, r0); 1804 1805 // Now check that handler read correct values 1806 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1807 CHECKREG(r5, 0x10000000); 1808 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14)); 1809 CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!) 1810 1811 //------------------------------------------------------- 1812 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1813 1814 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1815 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1816 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1817 CSYNC; 1818 1819 LD32(i1, 0x10000000); 1820 R1 = 0x33FA (Z); 1821 LD32(p2, DCPLB_DATA7); 1822 1823 X6_7: [ I1 ] = R1; // Exception should occur here 1824 1825 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1826 CSYNC; 1827 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1828 1829 // Now check that handler read correct values 1830 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1831 CHECKREG(r5, 0x10000000); 1832 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7)); 1833 CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!) 1834 1835 //------------------------------------------------------- 1836 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1837 1838 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1839 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1840 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1841 CSYNC; 1842 1843 LD32(i1, 0x10000000); 1844 R1 = 0x6FBE (Z); 1845 LD32(p2, DCPLB_DATA8); 1846 1847 X6_8: [ I1 ] = R1; // Exception should occur here 1848 1849 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1850 CSYNC; 1851 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1852 1853 // Now check that handler read correct values 1854 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1855 CHECKREG(r5, 0x10000000); 1856 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8)); 1857 CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!) 1858 1859 //------------------------------------------------------- 1860 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1861 1862 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1863 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1864 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1865 CSYNC; 1866 1867 LD32(i1, 0x10000000); 1868 R1 = 0x36A6 (Z); 1869 LD32(p2, DCPLB_DATA9); 1870 1871 X6_9: [ I1 ] = R1; // Exception should occur here 1872 1873 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1874 CSYNC; 1875 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1876 1877 // Now check that handler read correct values 1878 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1879 CHECKREG(r5, 0x10000000); 1880 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9)); 1881 CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!) 1882 1883 //------------------------------------------------------- 1884 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1885 1886 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1887 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1888 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1889 CSYNC; 1890 1891 LD32(i1, 0x10000000); 1892 R1 = 0x2DDA (Z); 1893 LD32(p2, DCPLB_DATA10); 1894 1895 X6_10: [ I1 ] = R1; // Exception should occur here 1896 1897 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1898 CSYNC; 1899 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1900 1901 // Now check that handler read correct values 1902 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1903 CHECKREG(r5, 0x10000000); 1904 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10)); 1905 CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!) 1906 1907 //------------------------------------------------------- 1908 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1909 1910 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1911 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1912 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1913 CSYNC; 1914 1915 LD32(i1, 0x10000000); 1916 R1 = 0x30E4 (Z); 1917 LD32(p2, DCPLB_DATA11); 1918 1919 X6_11: [ I1 ] = R1; // Exception should occur here 1920 1921 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1922 CSYNC; 1923 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1924 1925 // Now check that handler read correct values 1926 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1927 CHECKREG(r5, 0x10000000); 1928 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11)); 1929 CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!) 1930 1931 //------------------------------------------------------- 1932 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1933 1934 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1935 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1936 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1937 CSYNC; 1938 1939 LD32(i1, 0x10000000); 1940 R1 = 0x0586 (Z); 1941 LD32(p2, DCPLB_DATA12); 1942 1943 X6_12: [ I1 ] = R1; // Exception should occur here 1944 1945 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1946 CSYNC; 1947 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1948 1949 // Now check that handler read correct values 1950 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1951 CHECKREG(r5, 0x10000000); 1952 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12)); 1953 CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!) 1954 1955 //------------------------------------------------------- 1956 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1957 1958 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1959 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1960 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1961 CSYNC; 1962 1963 LD32(i1, 0x10000000); 1964 R1 = 0x148E (Z); 1965 LD32(p2, DCPLB_DATA13); 1966 1967 X6_13: [ I1 ] = R1; // Exception should occur here 1968 1969 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1970 CSYNC; 1971 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1972 1973 // Now check that handler read correct values 1974 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1975 CHECKREG(r5, 0x10000000); 1976 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13)); 1977 CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!) 1978 1979 //------------------------------------------------------- 1980 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 1981 1982 WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1983 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 1984 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 1985 CSYNC; 1986 1987 LD32(i1, 0x10000000); 1988 R1 = 0x42DC (Z); 1989 LD32(p2, DCPLB_DATA14); 1990 1991 X6_14: [ I1 ] = R1; // Exception should occur here 1992 1993 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 1994 CSYNC; 1995 WR_MMR(DCPLB_DATA6, 0, p0, r0); 1996 1997 // Now check that handler read correct values 1998 CHECKREG(r4,0x27); // supv and EXCPT_PROT 1999 CHECKREG(r5, 0x10000000); 2000 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14)); 2001 CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!) 2002 2003 //------------------------------------------------------- 2004 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2005 2006 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2007 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2008 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2009 CSYNC; 2010 2011 LD32(i1, 0x10000000); 2012 R1 = 0x5929 (Z); 2013 LD32(p2, DCPLB_DATA8); 2014 2015 X7_8: [ I1 ] = R1; // Exception should occur here 2016 2017 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2018 CSYNC; 2019 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2020 2021 // Now check that handler read correct values 2022 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2023 CHECKREG(r5, 0x10000000); 2024 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8)); 2025 CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!) 2026 2027 //------------------------------------------------------- 2028 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2029 2030 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2031 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2032 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2033 CSYNC; 2034 2035 LD32(i1, 0x10000000); 2036 R1 = 0x0C6D (Z); 2037 LD32(p2, DCPLB_DATA9); 2038 2039 X7_9: [ I1 ] = R1; // Exception should occur here 2040 2041 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2042 CSYNC; 2043 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2044 2045 // Now check that handler read correct values 2046 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2047 CHECKREG(r5, 0x10000000); 2048 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9)); 2049 CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!) 2050 2051 //------------------------------------------------------- 2052 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2053 2054 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2055 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2056 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2057 CSYNC; 2058 2059 LD32(i1, 0x10000000); 2060 R1 = 0x334E (Z); 2061 LD32(p2, DCPLB_DATA10); 2062 2063 X7_10: [ I1 ] = R1; // Exception should occur here 2064 2065 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2066 CSYNC; 2067 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2068 2069 // Now check that handler read correct values 2070 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2071 CHECKREG(r5, 0x10000000); 2072 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10)); 2073 CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!) 2074 2075 //------------------------------------------------------- 2076 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2077 2078 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2079 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2080 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2081 CSYNC; 2082 2083 LD32(i1, 0x10000000); 2084 R1 = 0x62FF (Z); 2085 LD32(p2, DCPLB_DATA11); 2086 2087 X7_11: [ I1 ] = R1; // Exception should occur here 2088 2089 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2090 CSYNC; 2091 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2092 2093 // Now check that handler read correct values 2094 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2095 CHECKREG(r5, 0x10000000); 2096 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11)); 2097 CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!) 2098 2099 //------------------------------------------------------- 2100 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2101 2102 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2103 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2104 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2105 CSYNC; 2106 2107 LD32(i1, 0x10000000); 2108 R1 = 0x1F56 (Z); 2109 LD32(p2, DCPLB_DATA12); 2110 2111 X7_12: [ I1 ] = R1; // Exception should occur here 2112 2113 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2114 CSYNC; 2115 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2116 2117 // Now check that handler read correct values 2118 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2119 CHECKREG(r5, 0x10000000); 2120 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12)); 2121 CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!) 2122 2123 //------------------------------------------------------- 2124 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2125 2126 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2127 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2128 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2129 CSYNC; 2130 2131 LD32(i1, 0x10000000); 2132 R1 = 0x2BE1 (Z); 2133 LD32(p2, DCPLB_DATA13); 2134 2135 X7_13: [ I1 ] = R1; // Exception should occur here 2136 2137 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2138 CSYNC; 2139 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2140 2141 // Now check that handler read correct values 2142 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2143 CHECKREG(r5, 0x10000000); 2144 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13)); 2145 CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!) 2146 2147 //------------------------------------------------------- 2148 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2149 2150 WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2151 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2152 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2153 CSYNC; 2154 2155 LD32(i1, 0x10000000); 2156 R1 = 0x1D70 (Z); 2157 LD32(p2, DCPLB_DATA14); 2158 2159 X7_14: [ I1 ] = R1; // Exception should occur here 2160 2161 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2162 CSYNC; 2163 WR_MMR(DCPLB_DATA7, 0, p0, r0); 2164 2165 // Now check that handler read correct values 2166 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2167 CHECKREG(r5, 0x10000000); 2168 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14)); 2169 CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!) 2170 2171 //------------------------------------------------------- 2172 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2173 2174 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2175 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2176 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2177 CSYNC; 2178 2179 LD32(i1, 0x10000000); 2180 R1 = 0x2620 (Z); 2181 LD32(p2, DCPLB_DATA9); 2182 2183 X8_9: [ I1 ] = R1; // Exception should occur here 2184 2185 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2186 CSYNC; 2187 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2188 2189 // Now check that handler read correct values 2190 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2191 CHECKREG(r5, 0x10000000); 2192 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9)); 2193 CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!) 2194 2195 //------------------------------------------------------- 2196 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2197 2198 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2199 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2200 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2201 CSYNC; 2202 2203 LD32(i1, 0x10000000); 2204 R1 = 0x26FB (Z); 2205 LD32(p2, DCPLB_DATA10); 2206 2207 X8_10: [ I1 ] = R1; // Exception should occur here 2208 2209 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2210 CSYNC; 2211 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2212 2213 // Now check that handler read correct values 2214 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2215 CHECKREG(r5, 0x10000000); 2216 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10)); 2217 CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!) 2218 2219 //------------------------------------------------------- 2220 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2221 2222 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2223 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2224 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2225 CSYNC; 2226 2227 LD32(i1, 0x10000000); 2228 R1 = 0x718F (Z); 2229 LD32(p2, DCPLB_DATA11); 2230 2231 X8_11: [ I1 ] = R1; // Exception should occur here 2232 2233 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2234 CSYNC; 2235 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2236 2237 // Now check that handler read correct values 2238 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2239 CHECKREG(r5, 0x10000000); 2240 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11)); 2241 CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!) 2242 2243 //------------------------------------------------------- 2244 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2245 2246 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2247 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2248 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2249 CSYNC; 2250 2251 LD32(i1, 0x10000000); 2252 R1 = 0x04B1 (Z); 2253 LD32(p2, DCPLB_DATA12); 2254 2255 X8_12: [ I1 ] = R1; // Exception should occur here 2256 2257 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2258 CSYNC; 2259 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2260 2261 // Now check that handler read correct values 2262 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2263 CHECKREG(r5, 0x10000000); 2264 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12)); 2265 CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!) 2266 2267 //------------------------------------------------------- 2268 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2269 2270 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2271 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2272 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2273 CSYNC; 2274 2275 LD32(i1, 0x10000000); 2276 R1 = 0x5358 (Z); 2277 LD32(p2, DCPLB_DATA13); 2278 2279 X8_13: [ I1 ] = R1; // Exception should occur here 2280 2281 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2282 CSYNC; 2283 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2284 2285 // Now check that handler read correct values 2286 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2287 CHECKREG(r5, 0x10000000); 2288 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13)); 2289 CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!) 2290 2291 //------------------------------------------------------- 2292 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2293 2294 WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2295 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2296 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2297 CSYNC; 2298 2299 LD32(i1, 0x10000000); 2300 R1 = 0x3305 (Z); 2301 LD32(p2, DCPLB_DATA14); 2302 2303 X8_14: [ I1 ] = R1; // Exception should occur here 2304 2305 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2306 CSYNC; 2307 WR_MMR(DCPLB_DATA8, 0, p0, r0); 2308 2309 // Now check that handler read correct values 2310 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2311 CHECKREG(r5, 0x10000000); 2312 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14)); 2313 CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!) 2314 2315 //------------------------------------------------------- 2316 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2317 2318 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2319 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2320 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2321 CSYNC; 2322 2323 LD32(i1, 0x10000000); 2324 R1 = 0x5690 (Z); 2325 LD32(p2, DCPLB_DATA10); 2326 2327 X9_10: [ I1 ] = R1; // Exception should occur here 2328 2329 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2330 CSYNC; 2331 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2332 2333 // Now check that handler read correct values 2334 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2335 CHECKREG(r5, 0x10000000); 2336 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10)); 2337 CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!) 2338 2339 //------------------------------------------------------- 2340 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2341 2342 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2343 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2344 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2345 CSYNC; 2346 2347 LD32(i1, 0x10000000); 2348 R1 = 0x5DC5 (Z); 2349 LD32(p2, DCPLB_DATA11); 2350 2351 X9_11: [ I1 ] = R1; // Exception should occur here 2352 2353 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2354 CSYNC; 2355 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2356 2357 // Now check that handler read correct values 2358 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2359 CHECKREG(r5, 0x10000000); 2360 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11)); 2361 CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!) 2362 2363 //------------------------------------------------------- 2364 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2365 2366 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2367 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2368 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2369 CSYNC; 2370 2371 LD32(i1, 0x10000000); 2372 R1 = 0x7809 (Z); 2373 LD32(p2, DCPLB_DATA12); 2374 2375 X9_12: [ I1 ] = R1; // Exception should occur here 2376 2377 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2378 CSYNC; 2379 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2380 2381 // Now check that handler read correct values 2382 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2383 CHECKREG(r5, 0x10000000); 2384 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12)); 2385 CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!) 2386 2387 //------------------------------------------------------- 2388 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2389 2390 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2391 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2392 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2393 CSYNC; 2394 2395 LD32(i1, 0x10000000); 2396 R1 = 0x1DDC (Z); 2397 LD32(p2, DCPLB_DATA13); 2398 2399 X9_13: [ I1 ] = R1; // Exception should occur here 2400 2401 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2402 CSYNC; 2403 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2404 2405 // Now check that handler read correct values 2406 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2407 CHECKREG(r5, 0x10000000); 2408 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13)); 2409 CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!) 2410 2411 //------------------------------------------------------- 2412 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2413 2414 WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2415 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2416 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2417 CSYNC; 2418 2419 LD32(i1, 0x10000000); 2420 R1 = 0x6B53 (Z); 2421 LD32(p2, DCPLB_DATA14); 2422 2423 X9_14: [ I1 ] = R1; // Exception should occur here 2424 2425 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2426 CSYNC; 2427 WR_MMR(DCPLB_DATA9, 0, p0, r0); 2428 2429 // Now check that handler read correct values 2430 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2431 CHECKREG(r5, 0x10000000); 2432 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14)); 2433 CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!) 2434 2435 //------------------------------------------------------- 2436 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2437 2438 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2439 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2440 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2441 CSYNC; 2442 2443 LD32(i1, 0x10000000); 2444 R1 = 0x7BCD (Z); 2445 LD32(p2, DCPLB_DATA11); 2446 2447 X10_11: [ I1 ] = R1; // Exception should occur here 2448 2449 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2450 CSYNC; 2451 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2452 2453 // Now check that handler read correct values 2454 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2455 CHECKREG(r5, 0x10000000); 2456 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11)); 2457 CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!) 2458 2459 //------------------------------------------------------- 2460 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2461 2462 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2463 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2464 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2465 CSYNC; 2466 2467 LD32(i1, 0x10000000); 2468 R1 = 0x63AA (Z); 2469 LD32(p2, DCPLB_DATA12); 2470 2471 X10_12: [ I1 ] = R1; // Exception should occur here 2472 2473 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2474 CSYNC; 2475 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2476 2477 // Now check that handler read correct values 2478 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2479 CHECKREG(r5, 0x10000000); 2480 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12)); 2481 CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!) 2482 2483 //------------------------------------------------------- 2484 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2485 2486 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2487 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2488 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2489 CSYNC; 2490 2491 LD32(i1, 0x10000000); 2492 R1 = 0x373B (Z); 2493 LD32(p2, DCPLB_DATA13); 2494 2495 X10_13: [ I1 ] = R1; // Exception should occur here 2496 2497 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2498 CSYNC; 2499 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2500 2501 // Now check that handler read correct values 2502 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2503 CHECKREG(r5, 0x10000000); 2504 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13)); 2505 CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!) 2506 2507 //------------------------------------------------------- 2508 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2509 2510 WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2511 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2512 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2513 CSYNC; 2514 2515 LD32(i1, 0x10000000); 2516 R1 = 0x5648 (Z); 2517 LD32(p2, DCPLB_DATA14); 2518 2519 X10_14: [ I1 ] = R1; // Exception should occur here 2520 2521 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2522 CSYNC; 2523 WR_MMR(DCPLB_DATA10, 0, p0, r0); 2524 2525 // Now check that handler read correct values 2526 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2527 CHECKREG(r5, 0x10000000); 2528 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14)); 2529 CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!) 2530 2531 //------------------------------------------------------- 2532 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2533 2534 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2535 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2536 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2537 CSYNC; 2538 2539 LD32(i1, 0x10000000); 2540 R1 = 0x6799 (Z); 2541 LD32(p2, DCPLB_DATA12); 2542 2543 X11_12: [ I1 ] = R1; // Exception should occur here 2544 2545 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2546 CSYNC; 2547 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2548 2549 // Now check that handler read correct values 2550 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2551 CHECKREG(r5, 0x10000000); 2552 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12)); 2553 CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!) 2554 2555 //------------------------------------------------------- 2556 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2557 2558 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2559 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2560 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2561 CSYNC; 2562 2563 LD32(i1, 0x10000000); 2564 R1 = 0x1452 (Z); 2565 LD32(p2, DCPLB_DATA13); 2566 2567 X11_13: [ I1 ] = R1; // Exception should occur here 2568 2569 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2570 CSYNC; 2571 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2572 2573 // Now check that handler read correct values 2574 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2575 CHECKREG(r5, 0x10000000); 2576 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13)); 2577 CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!) 2578 2579 //------------------------------------------------------- 2580 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2581 2582 WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2583 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2584 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2585 CSYNC; 2586 2587 LD32(i1, 0x10000000); 2588 R1 = 0x23D3 (Z); 2589 LD32(p2, DCPLB_DATA14); 2590 2591 X11_14: [ I1 ] = R1; // Exception should occur here 2592 2593 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2594 CSYNC; 2595 WR_MMR(DCPLB_DATA11, 0, p0, r0); 2596 2597 // Now check that handler read correct values 2598 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2599 CHECKREG(r5, 0x10000000); 2600 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14)); 2601 CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!) 2602 2603 //------------------------------------------------------- 2604 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2605 2606 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2607 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2608 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2609 CSYNC; 2610 2611 LD32(i1, 0x10000000); 2612 R1 = 0x1152 (Z); 2613 LD32(p2, DCPLB_DATA13); 2614 2615 X12_13: [ I1 ] = R1; // Exception should occur here 2616 2617 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2618 CSYNC; 2619 WR_MMR(DCPLB_DATA12, 0, p0, r0); 2620 2621 // Now check that handler read correct values 2622 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2623 CHECKREG(r5, 0x10000000); 2624 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13)); 2625 CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!) 2626 2627 //------------------------------------------------------- 2628 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2629 2630 WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2631 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2632 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2633 CSYNC; 2634 2635 LD32(i1, 0x10000000); 2636 R1 = 0x6E9D (Z); 2637 LD32(p2, DCPLB_DATA14); 2638 2639 X12_14: [ I1 ] = R1; // Exception should occur here 2640 2641 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2642 CSYNC; 2643 WR_MMR(DCPLB_DATA12, 0, p0, r0); 2644 2645 // Now check that handler read correct values 2646 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2647 CHECKREG(r5, 0x10000000); 2648 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14)); 2649 CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!) 2650 2651 //------------------------------------------------------- 2652 R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; 2653 2654 WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2655 WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0); 2656 WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0); 2657 CSYNC; 2658 2659 LD32(i1, 0x10000000); 2660 R1 = 0x6006 (Z); 2661 LD32(p2, DCPLB_DATA14); 2662 2663 X13_14: [ I1 ] = R1; // Exception should occur here 2664 2665 WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0); 2666 CSYNC; 2667 WR_MMR(DCPLB_DATA13, 0, p0, r0); 2668 2669 // Now check that handler read correct values 2670 CHECKREG(r4,0x27); // supv and EXCPT_PROT 2671 CHECKREG(r5, 0x10000000); 2672 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14)); 2673 CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!) 2674 2675 //------------------------------------------------------- 2676 User: 2677 NOP; 2678 dbg_pass; 2679
Indexes created Sat Feb 28 05:31:39 UTC 2026