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    Searched refs:DPG_WATERMARK_MASK_CONTROL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_mem_input.h 54 SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
109 uint32_t DPG_WATERMARK_MASK_CONTROL;
179 SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
180 SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
190 SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
224 SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
amdgpu_dce_mem_input.c 174 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
188 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
207 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
220 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
239 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
257 REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 870 #define DPG_WATERMARK_MASK_CONTROL 0x6cc8
radeon_cik.c 9415 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9419 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9424 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9427 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9432 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1131 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1138 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
amdgpu_dce_v11_0.c 1157 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1164 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

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