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    Searched refs:DP_DPCD_REV (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_dp.c 76 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_dp.c 2952 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3143 core_link_read_dpcd(link, DP_DPCD_REV,
3146 DP_DPCD_REV -
3147 DP_DPCD_REV];
3175 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3227 DP_DPCD_REV,
3315 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3345 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3349 DP_DPCD_REV];
    [all...]
amdgpu_dc_link_ddc.c 508 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 113 #define DP_DPCD_REV 0x000
1232 return dpcd[DP_DPCD_REV] >= 0x11 &&
1239 return dpcd[DP_DPCD_REV] >= 0x11 &&
1246 return dpcd[DP_DPCD_REV] >= 0x12 &&
1253 return dpcd[DP_DPCD_REV] >= 0x14 &&
1260 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dp_link_training.c 189 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
intel_lspcon.c 180 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
intel_dp.c 3178 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3205 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4307 * if it is set DP_DPCD_REV at 0000h could be at a value less than
4321 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4346 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4371 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4400 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4525 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4541 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/
drm_dp_helper.c 158 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
315 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
drm_dp_mst_topology.c 3523 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
3670 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd,
4634 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE);
5476 port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios_dp.c 348 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
  /src/sys/dev/ic/
anx_dp.c 569 ret = drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV, values,
592 if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios_dp.c 405 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
radeon_dp_mst.c 687 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_debugfs.c 2401 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
4347 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
nouveau_dispnv50_disp.c 1509 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);

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