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    Searched refs:DP_TRAINING_LANE0_SET (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dp_link_training.c 116 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
  /src/sys/dev/ic/
anx_dp.c 465 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
510 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
555 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atombios_dp.c 503 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios_dp.c 573 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 448 #define DP_TRAINING_LANE0_SET 0x103
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_dp.c 300 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
335 DP_TRAINING_LANE0_SET,
651 lane0_set_address = DP_TRAINING_LANE0_SET;

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