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    Searched refs:DR (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeSPARC_32.c 32 return push_inst(compiler, OR | D(dst) | S1(0) | IMM(imm), DR(dst));
34 FAIL_IF(push_inst(compiler, SETHI | D(dst) | ((imm >> 10) & 0x3fffff), DR(dst)));
35 return (imm & 0x3ff) ? push_inst(compiler, OR | D(dst) | S1(dst) | IMM_ARG | (imm & 0x3ff), DR(dst)) : SLJIT_SUCCESS;
52 return push_inst(compiler, OR | D(dst) | S1(0) | S2(src2), DR(dst));
60 return push_inst(compiler, AND | D(dst) | S1(src2) | IMM(0xff), DR(dst));
61 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst)));
62 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst));
72 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst)));
73 return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
81 return push_inst(compiler, XNOR | (flags & SET_FLAGS) | D(dst) | S1(0) | S2(src2), DR(dst) | (flags & SET_FLAGS))
    [all...]
sljitNativeMIPS_64.c 131 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
137 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
152 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
159 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \
173 return push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(dst), DR(dst));
181 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst)));
182 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(24), DR(dst));
184 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst));
196 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst)));
197 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(16), DR(dst))
    [all...]
sljitNativeMIPS_32.c 48 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
54 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
62 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
68 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \
83 return push_inst(compiler, ADDU | S(src2) | TA(0) | D(dst), DR(dst));
92 return push_inst(compiler, SEB | T(src2) | D(dst), DR(dst));
94 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst)));
95 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst));
98 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst));
111 return push_inst(compiler, SEH | T(src2) | D(dst), DR(dst))
    [all...]
sljitNativeMIPS_common.c 89 #define DR(dr) (reg_map[dr])
564 FAIL_IF(push_inst(compiler, ADDIU_W | S(SLJIT_SP) | T(SLJIT_SP) | IMM(-local_size), DR(SLJIT_SP)));
568 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size));
569 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | TA(0) | D(TMP_REG2), DR(TMP_REG2)));
570 FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP)));
590 FAIL_IF(push_inst(compiler, ADDU_W | SA(4) | TA(0) | D(SLJIT_S0), DR(SLJIT_S0)));
592 FAIL_IF(push_inst(compiler, ADDU_W | SA(5) | TA(0) | D(SLJIT_S1), DR(SLJIT_S1)));
594 FAIL_IF(push_inst(compiler, ADDU_W | SA(6) | TA(0) | D(SLJIT_S2), DR(SLJIT_S2)))
    [all...]
sljitNativeSPARC_common.c 118 #define DR(dr) (reg_map[dr])
539 ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS));
597 FAIL_IF(push_inst(compiler, SLL_W | D(arg2) | S1(OFFS_REG(arg)) | IMM_ARG | argw, DR(arg2)));
604 FAIL_IF(push_inst(compiler, ADD | D(TMP_REG3) | S1(TMP_REG3) | IMM(argw - compiler->cache_argw), DR(TMP_REG3)));
623 delay_slot = ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS;
629 return push_inst(compiler, ADD | D(base) | S1(base) | S2(arg2), DR(base));
791 FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? UMUL : SMUL) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R0)));
792 return push_inst(compiler, RDY | D(SLJIT_R1), DR(SLJIT_R1))
    [all...]
  /src/sys/arch/hpc/stand/hpcboot/sh3/dev/
sh_dev.cpp 138 DBG_BIT_PRINT(r16, DR);
sh3_dev.cpp 212 bitdisp(_reg_read_1(SH3_P##x##DR))
  /src/sys/arch/amd64/amd64/
db_disasm.c 98 #define DR 17 /* debug register */
237 /*21*/ { "mov", true, LONG, op2(DR,E), 0 }, /* since mod == 11 */
239 /*23*/ { "mov", true, LONG, op2(E,DR), 0 },
1431 case DR:
1432 db_printf("%%dr%d", f_reg(rex, regmodrm));
  /src/sys/arch/i386/i386/
db_disasm.c 80 #define DR 17 /* debug register */
204 /*21*/ { "mov", true, LONG, op2(DR,El), 0 },
206 /*23*/ { "mov", true, LONG, op2(El,DR), 0 },
1339 case DR:
1340 db_printf("%%dr%d", f_reg(regmodrm));
  /src/libexec/ld.aout_so/
ld.so.vax.uue 746 M4ND\0FA0>%504+!00F@$)$YE=$)31#H@;F5G9&DR+F,L=B`Q+C,@,3DY-R\P
874 MR```!```1)S(```$``!$H,@```0``$2DR```!```1*C(```$``!$K,@```0`
ld.so.sparc.uue 223 M@*(`"9`0``L"O__WF`,@`=`+/_^0(L`(@*(@`#*``"+2!&`LT`1@"("B`!DR
1571 M``!E@```95```&4X``!E&```90@``&3P``!DR```9*```&2```!D8```9$``
ld.so.arm.uue 1250 M`````"3`$`$`````),00`0`````DR!`!`````"3,$`$`E@``)-`0`0#,```D
2215 M`$PU,`!,-C,`3#<Q`$PS-P!,,C8P`$PR-C$`3#@V`$PX,0!,.3``3#DR`$PY
ld.so.i386.uue 352 M__^)$>E6^___B?:+A6S___^H0'0:@T40!(M5$(M*_(N%:/___V:)`>DR^___

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