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      1 /* -*-C++-*-	$NetBSD: sh_dev.cpp,v 1.5 2008/04/28 20:23:20 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <hpcboot.h>
     33 #include <hpcmenu.h>
     34 #include <console.h>
     35 
     36 #include <sh3/sh_mmu.h>
     37 #include <sh3/dev/sh_dev.h>
     38 
     39 #include <sh3/dev/sh.h>
     40 
     41 SHdev::SHdev()
     42 {
     43 
     44 	_menu = &HpcMenuInterface::Instance();
     45 	_cons = Console::Instance();
     46 }
     47 
     48 void
     49 SHdev::dump(uint8_t bit)
     50 {
     51 	uint32_t reg = 0;
     52 	int kmode;
     53 
     54 	DPRINTF((TEXT("DEBUG BIT: ")));
     55 	bitdisp(bit);
     56 
     57 	if (bit & DUMP_CPU) {
     58 		// Cache
     59 		MemoryManager_SHMMU::CacheDump();
     60 		// MMU
     61 		MemoryManager_SHMMU::MMUDump();
     62 		// Status register
     63 		kmode = SetKMode(1);
     64 		__asm(
     65 			"stc	sr, r0\n"
     66 			"mov.l	r0, @r4", &reg);
     67 		SetKMode(kmode);
     68 		DPRINTF((TEXT("SR: ")));
     69 		bitdisp(reg);
     70 	}
     71 
     72 	if (bit & DUMP_DEV) {
     73 		kmode = SetKMode(1);
     74 		print_stack_pointer();
     75 		// SCIF
     76 		scif_dump(HPC_PREFERENCE.serial_speed);
     77 		SetKMode(kmode);
     78 	}
     79 }
     80 
     81 void
     82 SHdev::print_stack_pointer(void)
     83 {
     84 	int sp;
     85 
     86 	__asm("mov.l	r15, @r4", &sp);
     87 	DPRINTF((TEXT("SP 0x%08x\n"), sp));
     88 }
     89 
     90 //
     91 // SH3/SH4 common functions.
     92 //
     93 // SCIF
     94 void
     95 SHdev::scif_dump(int bps)
     96 {
     97 	uint16_t r16;
     98 	uint32_t r;
     99 	int n;
    100 
    101 	print_stack_pointer();
    102 	DPRINTF((TEXT("<<<SCIF>>>\n")));
    103 	/* mode */
    104 	r = _scif_reg_read(SH3_SCSMR2);
    105 	n = 1 << ((r & SCSMR2_CKS) << 1);
    106 	DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"),
    107 	    r & SCSMR2_CHR ? 7 : 8,
    108 	    r & SCSMR2_PE  ? r & SCSMR2_OE ? "odd" : "even" : "non",
    109 	    r & SCSMR2_STOP ? 2 : 1,
    110 	    n));
    111 	/* bit rate */
    112 	r = _scif_reg_read(SH3_SCBRR2);
    113 	DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r, bps,
    114 	    32 * bps *(r + 1) * n));
    115 
    116 	/* control */
    117 #define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, SCSCR2_##m, #m)
    118 	DPRINTF((TEXT("SCSCR2: ")));
    119 	r = _scif_reg_read(SH3_SCSCR2);
    120 	DBG_BIT_PRINT(r, TIE);
    121 	DBG_BIT_PRINT(r, RIE);
    122 	DBG_BIT_PRINT(r, TE);
    123 	DBG_BIT_PRINT(r, RE);
    124 	DPRINTF((TEXT("CKE=%d\n"), r & SCSCR2_CKE));
    125 #undef	DBG_BIT_PRINT
    126 
    127 	/* status */
    128 #define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, SCSSR2_##m, #m)
    129 	r16 = _reg_read_2(SH3_SCSSR2);
    130 	DPRINTF((TEXT("SCSSR2: ")));
    131 	DBG_BIT_PRINT(r16, ER);
    132 	DBG_BIT_PRINT(r16, TEND);
    133 	DBG_BIT_PRINT(r16, TDFE);
    134 	DBG_BIT_PRINT(r16, BRK);
    135 	DBG_BIT_PRINT(r16, FER);
    136 	DBG_BIT_PRINT(r16, PER);
    137 	DBG_BIT_PRINT(r16, RDF);
    138 	DBG_BIT_PRINT(r16, DR);
    139 #undef	DBG_BIT_PRINT
    140 
    141 	/* FIFO control */
    142 #define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, SCFCR2_##m, #m)
    143 	r = _scif_reg_read(SH3_SCFCR2);
    144 	DPRINTF((TEXT("SCFCR2: ")));
    145 	DBG_BIT_PRINT(r, RTRG1);
    146 	DBG_BIT_PRINT(r, RTRG0);
    147 	DBG_BIT_PRINT(r, TTRG1);
    148 	DBG_BIT_PRINT(r, TTRG0);
    149 	DBG_BIT_PRINT(r, MCE);
    150 	DBG_BIT_PRINT(r, TFRST);
    151 	DBG_BIT_PRINT(r, RFRST);
    152 	DBG_BIT_PRINT(r, LOOP);
    153 	DPRINTF((TEXT("\n")));
    154 #undef	DBG_BIT_PRINT
    155 }
    156 
    157 // INTC
    158 void
    159 SHdev::icu_dump_priority(struct intr_priority *tab)
    160 {
    161 
    162 	DPRINTF((TEXT("<<<INTC>>>\n")));
    163 
    164 	DPRINTF((TEXT("----interrupt priority----\n")));
    165 	for (; tab->name; tab++) {
    166 		DPRINTF((TEXT("%-10S %d\n"), tab->name,
    167 		    (_reg_read_2(tab->reg) >> tab->shift) & SH_IPR_MASK));
    168 	}
    169 	DPRINTF((TEXT("--------------------------\n")));
    170 }
    171 
    172