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  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
stm32f469.dtsi 8 dsi: dsi@40016c00 { label
9 compatible = "st,stm32-dsi";
11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
ste-ab8505.dtsi 300 // supply for U8500 CSI/DSI; VANA LDO
316 dsi@a0351000 {
319 dsi@a0352000 {
322 dsi@a0353000 {
ste-href.dtsi 263 regulator-name = "V-CSI/DSI";
bcm283x.dtsi 92 * platform's oscillator. However, the DSI
93 * pixel clocks come from the DSI analog PHY.
358 dsi0: dsi@7e209000 {
438 dsi1: dsi@7e700000 {
ste-ab8500.dtsi 364 // supply for U8500 CSI/DSI; VANA LDO
380 dsi@a0351000 {
383 dsi@a0352000 {
386 dsi@a0353000 {
ste-snowball.dts 461 regulator-name = "V-CSI/DSI";
ste-ux500-samsung-golden.dts 332 dsi@a0351000 {
581 /* Mux in VSI0 used for DSI TE */
ste-ux500-samsung-kyle.dts 435 dsi@a0351000 {
481 /* Mux in VSI0 used for DSI TE */
ste-ux500-samsung-skomer.dts 426 dsi@a0351000 {
479 /* Mux in VSI0 used for DSI TE */
ste-dbx5x0.dtsi 1100 dsi0: dsi@a0351000 {
1101 compatible = "ste,mcde-dsi";
1108 dsi1: dsi@a0352000 {
1109 compatible = "ste,mcde-dsi";
1116 dsi2: dsi@a0353000 {
1117 compatible = "ste,mcde-dsi";
1119 /* This DSI port only has the Low Power / Energy Save clock */
qcom-apq8064.dtsi 1249 compatible = "qcom,mdss-dsi-ctrl";
1250 label = "MDSS DSI CTRL->0";
1297 dsi0_phy: dsi-phy@4700200 {
1298 compatible = "qcom,dsi-phy-28nm-8960";
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/
r8a779a0-falcon-csi-dsi.dtsi 3 * Device Tree Source for the Falcon CSI/DSI sub-board
32 label = "csi-dsi-sub-board-id";
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
stm32mp1-clks.h 72 #define DSI 57
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8qxp-colibri.dtsi 289 /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-j721e-common-proc-board.dts 563 * VP2 - DSI
  /src/libexec/ld.aout_so/
ld.so.sparc.uue 744 M!>`,T`)``("B(``R@``*T$R``#"``">P!@`1T@(``+`&(`&2)``)DSI@`A"`
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display.c 1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
7003 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
8190 /* DPLL not used with DSI, but still need the rest set up */
8207 /* DPLL not used with DSI, but still need the rest set up */
8230 /* No need to actually set up the DPLL with DSI */
8331 /* No need to actually set up the DPLL with DSI */
9066 /* In case of DSI, DPLL will not be used */
9177 /* In case of DSI, DPLL will not be used *
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