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    Searched refs:ENABLE_L1_TLB (Results 1 - 25 of 25) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 131 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
316 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_gfxhub_v2_0.c 126 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
301 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_mmhub_v2_0.c 113 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
292 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_mmhub_v1_0.c 148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
350 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_gmc_v7_0.c 640 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
761 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_gmc_v8_0.c 861 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
999 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
amdgpu_mmhub_v9_4.c 195 ENABLE_L1_TLB, 1);
419 ENABLE_L1_TLB, 0);
sid.h 479 #define ENABLE_L1_TLB (1 << 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_hubp.h 404 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
602 type ENABLE_L1_TLB;\
amdgpu_dcn10_hubp.c 811 ENABLE_L1_TLB, 1,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_hwseq.h 710 type ENABLE_L1_TLB;\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 351 ENABLE_L1_TLB, 1,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv770d.h 467 #define ENABLE_L1_TLB (1 << 0)
radeon_rv770.c 921 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
998 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
nid.h 181 #define ENABLE_L1_TLB (1 << 0)
cikd.h 602 #define ENABLE_L1_TLB (1 << 0)
sid.h 477 #define ENABLE_L1_TLB (1 << 0)
evergreend.h 957 #define ENABLE_L1_TLB (1 << 0)
r600d.h 334 #define ENABLE_L1_TLB (1 << 0)
radeon_ni.c 1295 ENABLE_L1_TLB |
radeon_r600.c 1182 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1274 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
radeon_evergreen.c 2421 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
2504 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
radeon_si.c 4306 ENABLE_L1_TLB |
radeon_cik.c 5460 ENABLE_L1_TLB |
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 80 ENABLE_L1_TLB, 1,

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