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Searched refs:ENABLE_L2_CACHE (Results 1 - 20 of 20) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c	`151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 324 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_gfxhub_v2_0.c	`145 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 307 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_mmhub_v2_0.c	`132 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 299 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_mmhub_v1_0.c	`171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 360 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_gmc_v7_0.c	`648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 767 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_gmc_v8_0.c	`869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 1005 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);`
amdgpu_mmhub_v9_4.c	`221 ENABLE_L2_CACHE, 1); 431 ENABLE_L2_CACHE, 0);`
sid.h	`374 #define ENABLE_L2_CACHE (1 << 0)`
/src/sys/external/bsd/drm2/dist/drm/radeon/
rv770d.h	`645 #define ENABLE_L2_CACHE (1 << 0)`
radeon_rv770.c	`915 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \| 992 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|`
nid.h	`107 #define ENABLE_L2_CACHE (1 << 0)`
cikd.h	`490 #define ENABLE_L2_CACHE (1 << 0)`
sid.h	`372 #define ENABLE_L2_CACHE (1 << 0)`
evergreend.h	`1153 #define ENABLE_L2_CACHE (1 << 0)`
r600d.h	`590 #define ENABLE_L2_CACHE (1 << 0)`
radeon_ni.c	`1301 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \|`
radeon_r600.c	`1176 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \| 1268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|`
radeon_evergreen.c	`2415 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \| 2498 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|`
radeon_si.c	`4312 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \|`
radeon_cik.c	`5466 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \|`

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