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    Searched refs:ETH_CTL (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/at91/
at91emac.c 144 EMAC_WRITE(ETH_CTL, 0); // disable everything
232 ctl = EMAC_READ(ETH_CTL); // get current control register value
233 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
235 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
330 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
347 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
472 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
692 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
709 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
726 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everythin
    [all...]
at91emacreg.h 36 #define ETH_CTL 0x00U /* 0x00: Control Register */
  /src/sys/dev/cadence/
if_cemac.c 168 CEMAC_WRITE(ETH_CTL, 0); // disable everything
291 ctl = CEMAC_READ(ETH_CTL);
293 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
297 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
436 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
630 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
954 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX;
955 CEMAC_WRITE(ETH_CTL, ctl);
956 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__,
957 CEMAC_READ(ETH_CTL)));
    [all...]
cemacreg.h 39 #define ETH_CTL 0x00U /* Control Register */

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