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    Searched refs:FMT_FRAME_RANDOM_ENABLE (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_opp.c 177 FMT_FRAME_RANDOM_ENABLE, 0,
244 FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
dce_opp.h 99 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
170 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
215 type FMT_FRAME_RANDOM_ENABLE; \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 77 FMT_FRAME_RANDOM_ENABLE, 0,
140 FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
dcn10_opp.h 79 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
113 type FMT_FRAME_RANDOM_ENABLE; \
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
amdgpu_dce_v11_0.c 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
593 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sid.h 2112 #define FMT_FRAME_RANDOM_ENABLE (1 << 13)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 996 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
evergreend.h 1384 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
r600d.h 1253 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
radeon_cik.c 8839 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8847 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8856 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
radeon_evergreen.c 1333 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
1341 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

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