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Searched refs:FMT_HIGHPASS_RANDOM_ENABLE (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_opp.c	`176 FMT_HIGHPASS_RANDOM_ENABLE, 0, 243 FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,`
dce_opp.h	`98 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 169 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 214 type FMT_HIGHPASS_RANDOM_ENABLE; \`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c	`76 FMT_HIGHPASS_RANDOM_ENABLE, 0, 138 FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,`
dcn10_opp.h	`78 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 112 type FMT_HIGHPASS_RANDOM_ENABLE; \`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c	`543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);`
amdgpu_dce_v11_0.c	`569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);`
sid.h	`2114 #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)`
/src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h	`998 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)`
evergreend.h	`1386 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)`
r600d.h	`1255 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)`
radeon_cik.c	`8839 tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \| 8847 tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \| 8856 tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|`
radeon_evergreen.c	`1333 tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \| 1341 tmp \|= (FMT_FRAME_RANDOM_ENABLE \| FMT_HIGHPASS_RANDOM_ENABLE \|`

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