| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v9_4.c | 38 #include "gc/gc_9_4_1_offset.h"
39 #include "gc/gc_9_4_1_sh_mask.h"
47 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
48 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
50 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
51 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
52 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
54 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
55 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
57 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 }
[all...] |
| amdgpu_gfxhub_v1_0.c | 31 #include "gc/gc_9_0_offset.h"
32 #include "gc/gc_9_0_sh_mask.h"
33 #include "gc/gc_9_0_default.h"
40 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
50 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
53 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
68 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
70 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
[all...] |
| amdgpu_gfxhub_v2_0.c | 32 #include "gc/gc_10_1_0_offset.h"
33 #include "gc/gc_10_1_0_sh_mask.h"
34 #include "gc/gc_10_1_0_default.h"
41 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
51 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
61 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
64 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
79 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
[all...] |
| amdgpu_gfx_v9_0.c | 42 #include "gc/gc_9_0_offset.h"
43 #include "gc/gc_9_0_sh_mask.h"
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800)
[all...] |
| amdgpu_gfx_v10_0.c | 41 #include "gc/gc_10_1_0_offset.h"
42 #include "gc/gc_10_1_0_sh_mask.h"
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4)
[all...] |
| amdgpu_mes_v10_1.c | 34 #include "gc/gc_10_1_0_offset.h"
35 #include "gc/gc_10_1_0_sh_mask.h"
197 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
199 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
202 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
206 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL);
209 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data);
213 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
215 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
221 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data)
[all...] |
| amdgpu_gfxhub_v1_1.c | 31 #include "gc/gc_9_2_1_offset.h"
32 #include "gc/gc_9_2_1_sh_mask.h"
38 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
68 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
|
| amdgpu_amdkfd_gfx_v10.c | 30 #include "gc/gc_10_1_0_offset.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
139 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
140 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
204 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
242 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
278 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
281 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
288 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
317 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO)
[all...] |
| amdgpu_amdkfd_gfx_v9.c | 31 #include "gc/gc_9_0_offset.h"
32 #include "gc/gc_9_0_sh_mask.h"
135 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
136 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
214 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
268 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
271 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
278 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
307 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
309 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI)
[all...] |
| amdgpu_psp_v10_0.c | 42 #include "gc/gc_9_1_offset.h"
258 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
259 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
264 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
265 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
270 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
271 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
276 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
277 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
282 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR)
[all...] |
| amdgpu_soc15.c | 44 #include "gc/gc_9_0_offset.h"
45 #include "gc/gc_9_0_sh_mask.h"
208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v))
[all...] |
| amdgpu_psp_v12_0.c | 38 #include "gc/gc_9_0_offset.h"
362 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
363 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
368 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
369 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
374 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
375 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
380 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
381 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
386 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR)
[all...] |
| amdgpu_nv.c | 44 #include "gc/gc_10_1_0_offset.h"
45 #include "gc/gc_10_1_0_sh_mask.h"
108 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
109 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
122 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
123 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
151 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
192 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
193 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
194 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}
[all...] |
| amdgpu_psp_v3_1.c | 43 #include "gc/gc_9_0_offset.h"
438 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
439 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
444 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
445 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
450 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
451 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
456 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
457 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
462 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR)
[all...] |
| amdgpu_sdma_v5_0.c | 38 #include "gc/gc_10_1_0_offset.h"
39 #include "gc/gc_10_1_0_sh_mask.h"
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000)
[all...] |
| amdgpu_psp_v11_0.c | 41 #include "gc/gc_9_0_offset.h"
591 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
592 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
597 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
598 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
603 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
604 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
609 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
610 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
615 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR)
[all...] |
| amdgpu_discovery.c | 50 [GC_HWID] = "GC",
225 info = &bhdr->table_list[GC];
232 DRM_ERROR("invalid gc data table checksum\n");
390 le16_to_cpu(bhdr->table_list[GC].offset));
|
| /src/sys/external/bsd/compiler_rt/dist/lib/asan/ |
| asan_fake_stack.h | 154 void GC(uptr real_stack);
|
| asan_fake_stack.cc | 92 GC(real_stack);
142 NOINLINE void FakeStack::GC(uptr real_stack) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| discovery.h | 36 GC,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega10_powertune.c | 950 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
965 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1001 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1010 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1062 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1073 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1112 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1121 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1171 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
|
| /src/libexec/ld.aout_so/ |
| ld.so.arm.uue | 192 M<`OE0%`+Y0A0E>4``%7C;___&D2`&^4``%CC%0``&CR0&^4``%GC"`"@X?"O
384 M-0#K`$!0XAS__QJL`!OEGC4`Z[0P&^4``%GC`3"#$P``4^,&`*`1\*\;&<!P
419 M"""3X@,```H(,9+E!`!3X0`PX`,(,8(%+)$;Y0R0V>4(`!GC`P``"BS!&^40
428 MD4OE-,$;Y0%`W.1L00OE-,$+Y6R1&^5H`%GCH@``"C,``,HY`%GC'0``RC$`
432 M`%3CF0``"D\`5./P```*#0(`ZFR1&^5C`%GCAP``"@(``,I8`%GC:P$`"@8"
883 M5!R3Y0`@D>4%`*#A`!"@X\P?`.L``%GC"0``"@``E.54/)#E##"3Y0``4^,7
901 M`.L``%GC"0``"@``E.54/)#E##"3Y0``4^,0```*!1"@X0D@H.$/X*#A`_"@
903 M#^"@$0/PH!$P@!OE``!8XP(```H`,)CE``!3XQ4``!H``%GC"0``&@!@X.,X
1211 M``!0XP6`H+$(`*#A````Z@8`H.$`8*#A.)`;Y2B`&^4``%GC`1!(X@4``!I,
|
