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      1 /*	$NetBSD: amdgpu_gfxhub_v1_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2018 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #include <sys/cdefs.h>
     26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfxhub_v1_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
     27 
     28 #include "amdgpu.h"
     29 #include "gfxhub_v1_1.h"
     30 
     31 #include "gc/gc_9_2_1_offset.h"
     32 #include "gc/gc_9_2_1_sh_mask.h"
     33 
     34 #include "soc15_common.h"
     35 
     36 int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
     37 {
     38 	u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
     39 	u32 max_region =
     40 		REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
     41 	u32 max_num_physical_nodes   = 0;
     42 	u32 max_physical_node_id     = 0;
     43 
     44 	switch (adev->asic_type) {
     45 	case CHIP_VEGA20:
     46 		max_num_physical_nodes   = 4;
     47 		max_physical_node_id     = 3;
     48 		break;
     49 	case CHIP_ARCTURUS:
     50 		max_num_physical_nodes   = 8;
     51 		max_physical_node_id     = 7;
     52 		break;
     53 	default:
     54 		return -EINVAL;
     55 	}
     56 
     57 	/* PF_MAX_REGION=0 means xgmi is disabled */
     58 	if (max_region) {
     59 		adev->gmc.xgmi.num_physical_nodes = max_region + 1;
     60 		if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
     61 			return -EINVAL;
     62 
     63 		adev->gmc.xgmi.physical_node_id =
     64 			REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
     65 		if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
     66 			return -EINVAL;
     67 		adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
     68 			RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
     69 			MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
     70 	}
     71 
     72 	return 0;
     73 }
     74