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    Searched refs:GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT (Results 1 - 2 of 2) sorted by relevancy

/src/sys/dev/ic/
dwc_eqos_reg.h	250 #define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18 251 #define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT)
dwc_eqos.c	625 val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT;

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