1 /* $NetBSD: dwc_eqos_reg.h,v 1.10 2023/11/13 15:08:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2022 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * DesignWare Ethernet Quality-of-Service controller 31 */ 32 33 #ifndef _DWC_EQOS_REG_H 34 #define _DWC_EQOS_REG_H 35 36 #define GMAC_MAC_CONFIGURATION 0x0000 37 #define GMAC_MAC_CONFIGURATION_CST (1U << 21) 38 #define GMAC_MAC_CONFIGURATION_ACS (1U << 20) 39 #define GMAC_MAC_CONFIGURATION_BE (1U << 18) 40 #define GMAC_MAC_CONFIGURATION_JD (1U << 17) 41 #define GMAC_MAC_CONFIGURATION_JE (1U << 16) 42 #define GMAC_MAC_CONFIGURATION_PS (1U << 15) 43 #define GMAC_MAC_CONFIGURATION_FES (1U << 14) 44 #define GMAC_MAC_CONFIGURATION_DM (1U << 13) 45 #define GMAC_MAC_CONFIGURATION_DCRS (1U << 9) 46 #define GMAC_MAC_CONFIGURATION_TE (1U << 1) 47 #define GMAC_MAC_CONFIGURATION_RE (1U << 0) 48 #define GMAC_MAC_EXT_CONFIGURATION 0x0004 49 #define GMAC_MAC_PACKET_FILTER 0x0008 50 #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) 51 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) 52 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) 53 #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) 54 #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) 55 #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) 56 #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) 57 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) 58 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C 59 #define GMAC_MAC_HASH_TABLE_REG0 0x0010 60 #define GMAC_MAC_HASH_TABLE_REG1 0x0014 61 #define GMAC_MAC_VLAN_TAG 0x0050 62 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070 63 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 64 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1) 65 #define GMAC_MAC_RX_FLOW_CTRL 0x0090 66 #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0) 67 #define GMAC_RXQ_CTRL0 0x00A0 68 #define GMAC_RXQ_CTRL0_EN_MASK 0x3 69 #define GMAC_RXQ_CTRL0_EN_AVB 0x1 70 #define GMAC_RXQ_CTRL0_EN_DCB 0x2 71 #define GMAC_RXQ_CTRL1 0x00A4 72 #define GMAC_RXQ_CTRL2 0x00A8 73 #define GMAC_MAC_INTERRUPT_STATUS 0x00B0 74 #define GMAC_MAC_INTERRUPT_ENABLE 0x00B4 75 #define GMAC_MAC_RX_TX_STATUS 0x00B8 76 #define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8) 77 #define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5) 78 #define GMAC_MAC_RX_TX_STATUS_LCOL (1U << 4) 79 #define GMAC_MAC_RX_TX_STATUS_EXDEF (1U << 3) 80 #define GMAC_MAC_RX_TX_STATUS_LCARR (1U << 2) 81 #define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1) 82 #define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0) 83 #define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0 84 #define GMAC_MAC_RWK_PACKET_FILTER 0x00C4 85 #define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0 86 #define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4 87 #define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8 88 #define GMAC_MAC_1US_TIC_COUNTER 0x00DC 89 #define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8 90 #define GMAC_MAC_VERSION 0x0110 91 #define GMAC_MAC_VERSION_USERVER_SHIFT 8 92 #define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) 93 #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU 94 #define GMAC_MAC_DEBUG 0x0114 95 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) 96 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE __BITS(10,6) 97 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE __BITS(4,0) 98 #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 99 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 100 #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 101 #define GMAC_MAC_MDIO_ADDRESS 0x0200 102 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 103 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 104 #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 105 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 106 #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 107 #define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 108 #define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 109 #define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 110 #define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 111 #define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 112 #define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 113 #define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 114 #define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4) 115 #define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2 116 #define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 117 #define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 118 #define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1) 119 #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0) 120 #define GMAC_MAC_MDIO_DATA 0x0204 121 #define GMAC_MAC_CSR_SW_CTRL 0x0230 122 #define GMAC_MAC_ADDRESS0_HIGH 0x0300 123 #define GMAC_MAC_ADDRESS0_HIGH_AE (1U << 31) 124 #define GMAC_MAC_ADDRESS0_LOW 0x0304 125 #define GMAC_MMC_CONTROL 0x0700 126 #define GMAC_MMC_CONTROL_UCDBC (1U << 8) 127 #define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5) 128 #define GMAC_MMC_CONTROL_CNTPRST (1U << 4) 129 #define GMAC_MMC_CONTROL_CNTFREEZ (1U << 3) 130 #define GMAC_MMC_CONTROL_RSTONRD (1U << 2) 131 #define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1) 132 #define GMAC_MMC_CONTROL_CNTRST (1U << 0) 133 #define GMAC_MMC_RX_INTERRUPT 0x0704 134 #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS (1U << 21) 135 #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS (1U << 18) 136 #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS (1U << 5) 137 #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS (1U << 4) 138 #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS (1U << 2) 139 #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS (1U << 1) 140 #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS (1U << 0) 141 #define GMAC_MMC_TX_INTERRUPT 0x0708 142 #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS (1U << 21) 143 #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS (1U << 20) 144 #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS (1U << 19) 145 #define GMAC_MMC_TX_INTERRUPT_TXFLOWERPIS (1U << 13) 146 #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS (1U << 1) 147 #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS (1U << 0) 148 /* Use GMAC_MMC_RX_INTERRUPT_MASK bits for GMAC_MMC_RX_INTERRUPT_MASK */ 149 #define GMAC_MMC_RX_INTERRUPT_MASK 0x070C 150 /* Use GMAC_MMC_TX_INTERRUPT_MASK bits for GMAC_MMC_TX_INTERRUPT_MASK */ 151 #define GMAC_MMC_TX_INTERRUPT_MASK 0x0710 152 #define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714 153 #define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718 154 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748 155 #define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760 156 #define GMAC_TX_OCTET_COUNT_GOOD 0x0764 157 #define GMAC_TX_PACKET_COUNT_GOOD 0x0768 158 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780 159 #define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784 160 #define GMAC_RX_OCTET_COUNT_GOOD 0x0788 161 #define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790 162 #define GMAC_RX_CRC_ERROR_PACKETS 0x0794 163 #define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8 164 #define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4 165 #define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800 166 #define GMAC_MMC_IPC_RX_INTERRUPT 0x0808 167 #define GMAC_RXIPV4_GOOD_PACKETS 0x0810 168 #define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814 169 #define GMAC_RXIPV6_GOOD_PACKETS 0x0824 170 #define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828 171 #define GMAC_RXUDP_ERROR_PACKETS 0x0834 172 #define GMAC_RXTCP_ERROR_PACKETS 0x083C 173 #define GMAC_RXICMP_ERROR_PACKETS 0x0844 174 #define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854 175 #define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868 176 #define GMAC_RXUDP_ERROR_OCTETS 0x0874 177 #define GMAC_RXTCP_ERROR_OCTETS 0x087C 178 #define GMAC_RXICMP_ERROR_OCTETS 0x0884 179 #define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00 180 #define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04 181 #define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08 182 #define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C 183 #define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10 184 #define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14 185 #define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18 186 #define GMAC_MAC_TIMESTAMP_STATUS 0x0B20 187 #define GMAC_MAC_TX_TS_STATUS_NS 0x0B30 188 #define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34 189 #define GMAC_MAC_AUXILIARY_CONTROL 0x0B40 190 #define GMAC_MAC_AUXILIARY_TS_NS 0x0B48 191 #define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C 192 #define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58 193 #define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C 194 #define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68 195 #define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C 196 #define GMAC_MAC_PPS_CONTROL 0x0B70 197 #define GMAC_MTL_DBG_CTL 0x0C08 198 #define GMAC_MTL_DBG_STS 0x0C0C 199 #define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10 200 #define GMAC_MTL_INTERRUPT_STATUS 0x0C20 201 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17) 202 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0) 203 #define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00 204 #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS __BITS(24,16) 205 #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC __BITS(6,4) 206 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 207 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 208 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 209 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1) 210 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0) 211 #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04 212 #define GMAC_MTL_TXQ0_DEBUG 0x0D08 213 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C 214 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24) 215 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16) 216 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8) 217 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0) 218 #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30 219 #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS __BITS(29,20) 220 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD __BITS(19,14) 221 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA __BITS(13,8) 222 #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1U << 7) 223 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5) 224 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4) 225 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3) 226 #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34 227 #define GMAC_MTL_RXQ0_DEBUG 0x0D38 228 #define GMAC_DMA_MODE 0x1000 229 #define GMAC_DMA_MODE_SWR (1U << 0) 230 #define GMAC_DMA_SYSBUS_MODE 0x1004 231 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 232 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xfU << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) 233 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 234 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xfU << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) 235 #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14) 236 #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11) 237 #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3) 238 #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2) 239 #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1) 240 #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0) 241 #define GMAC_DMA_INTERRUPT_STATUS 0x1008 242 #define GMAC_DMA_DEBUG_STATUS0 0x100C 243 #define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040 244 #define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n)) 245 #define GMAC_RWK_FILTER01_CRC 0x10D0 246 #define GMAC_RWK_FILTER23_CRC 0x10D4 247 #define GMAC_RWK_FILTER_OFFSET 0x10D8 248 #define GMAC_RWK_FILTER_COMMAND 0x10DC 249 #define GMAC_DMA_CHAN0_CONTROL 0x1100 250 #define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18 251 #define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT) 252 #define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16) 253 #define GMAC_DMA_CHAN0_TX_CONTROL 0x1104 254 #define GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT 16 255 #define GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_MASK (0x3FU << GMAC_DMA_CHAN0_TX_CONTROL_TXPBL_SHIFT) 256 #define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4) 257 #define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0) 258 #define GMAC_DMA_CHAN0_RX_CONTROL 0x1108 259 #define GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT 16 260 #define GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_MASK (0x3FU << GMAC_DMA_CHAN0_RX_CONTROL_RXPBL_SHIFT) 261 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1 262 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT) 263 #define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0) 264 #define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110 265 #define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114 266 #define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118 267 #define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C 268 #define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120 269 #define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128 270 #define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C 271 #define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130 272 #define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134 273 #define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15) 274 #define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14) 275 #define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12) 276 #define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6) 277 #define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0) 278 #define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138 279 #define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C 280 #define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144 281 #define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C 282 #define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154 283 #define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C 284 #define GMAC_DMA_CHAN0_STATUS 0x1160 285 #define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15) 286 #define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14) 287 #define GMAC_DMA_CHAN0_STATUS_FB (1U << 12) 288 #define GMAC_DMA_CHAN0_STATUS_RI (1U << 6) 289 #define GMAC_DMA_CHAN0_STATUS_TI (1U << 0) 290 291 struct eqos_dma_desc { 292 uint32_t tdes0; 293 uint32_t tdes1; 294 uint32_t tdes2; 295 #define EQOS_TDES2_TX_IOC (1U << 31) /* TX */ 296 uint32_t tdes3; 297 #define EQOS_TDES3_TX_OWN (1U << 31) /* TX */ 298 #define EQOS_TDES3_TX_FD (1U << 29) /* TX */ 299 #define EQOS_TDES3_TX_LD (1U << 28) /* TX */ 300 #define EQOS_TDES3_TX_DE (1U << 23) /* TX (WB) */ 301 #define EQOS_TDES3_TX_ES (1U << 15) /* TX (WB) */ 302 #define EQOS_TDES3_RX_OWN (1U << 31) /* RX */ 303 #define EQOS_TDES3_RX_IOC (1U << 30) /* RX */ 304 #define EQOS_TDES3_RX_BUF1V (1U << 24) /* RX */ 305 #define EQOS_TDES3_RX_CTXT (1U << 30) /* RX (WB) */ 306 #define EQOS_TDES3_RX_FD (1U << 29) /* RX (WB) */ 307 #define EQOS_TDES3_RX_LD (1U << 28) /* RX (WB) */ 308 #define EQOS_TDES3_RX_CE (1U << 24) /* RX (WB) */ 309 #define EQOS_TDES3_RX_GP (1U << 23) /* RX (WB) */ 310 #define EQOS_TDES3_RX_RWT (1U << 22) /* RX (WB) */ 311 #define EQOS_TDES3_RX_OE (1U << 21) /* RX (WB) */ 312 #define EQOS_TDES3_RX_RE (1U << 20) /* RX (WB) */ 313 #define EQOS_TDES3_RX_DE (1U << 19) /* RX (WB) */ 314 #define EQOS_TDES3_RX_ES (1U << 15) /* RX (WB) */ 315 #define EQOS_TDES3_RX_LENGTH_MASK 0x7FFFU /* RX */ 316 } __aligned (64); 317 318 #endif /* !_DWC_EQOS_REG_H */ 319
Indexes created Mon Sep 22 13:09:51 GMT 2025