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    Searched refs:GRBM_GFX_INDEX (Results 1 - 24 of 24) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
cik_regs.h 71 #define GRBM_GFX_INDEX 0x30800
kfd_dbgdev.c 658 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
672 /* Restore the GRBM_GFX_INDEX register */
682 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_4.c 104 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
107 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
111 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
114 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
117 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
120 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
amdgpu_vce_v4_0.c 710 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
722 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
727 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
732 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
914 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
933 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
amdgpu_amdkfd_gfx_v10.c 759 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
761 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
763 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
amdgpu_amdkfd_gfx_v8.c 622 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
624 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
626 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
amdgpu_amdkfd_gfx_v9.c 689 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
691 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
693 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
amdgpu_gfx_v10_0.c 1501 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1504 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1514 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
amdgpu_vce_v3_0.c 616 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
828 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
amdgpu_gfx_v8_0.c 3428 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3430 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3433 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3435 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3438 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3440 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3606 /* GRBM_GFX_INDEX has a different offset on VI */
3612 /* GRBM_GFX_INDEX has a different offset on VI */
amdgpu_gfx_v9_0.c 2342 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2344 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2347 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2349 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2352 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2354 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
amdgpu_gfx_v6_0.c 1312 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1314 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1459 /* GRBM_GFX_INDEX has a different offset on SI */
1464 /* GRBM_GFX_INDEX has a different offset on SI */
sid.h 999 #define GRBM_GFX_INDEX 0x200B
amdgpu_gfx_v7_0.c 1602 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1604 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1776 /* GRBM_GFX_INDEX has a different offset on CI+ */
1782 /* GRBM_GFX_INDEX has a different offset on CI+ */
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cypress_dpm.c 132 WREG32(GRBM_GFX_INDEX, 0xC0000000);
159 WREG32(GRBM_GFX_INDEX, 0xC0000000);
193 WREG32(GRBM_GFX_INDEX, 0xC0000000);
214 WREG32(GRBM_GFX_INDEX, 0xC0000000);
radeon_ni.c 1102 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1122 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1131 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
nid.h 297 #define GRBM_GFX_INDEX 0x802C
cikd.h 1629 #define GRBM_GFX_INDEX 0x30800
sid.h 1000 #define GRBM_GFX_INDEX 0x802C
radeon_evergreen.c 3470 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3491 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3500 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
evergreend.h 414 #define GRBM_GFX_INDEX 0x802C
radeon_si.c 2971 WREG32(GRBM_GFX_INDEX, data);
4430 case GRBM_GFX_INDEX:
radeon_evergreen_cs.c 3264 case GRBM_GFX_INDEX:
radeon_cik.c 3065 WREG32(GRBM_GFX_INDEX, data);

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