HomeSort by: relevance | last modified time | path
    Searched refs:GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
amdgpu_irq_service_dce110.c 133 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
134 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
amdgpu_irq_service_dce80.c 137 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
138 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 2077 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
amdgpu_dce_v10_0.c 3154 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
amdgpu_dce_v11_0.c 3280 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
amdgpu_dce_v6_0.c 3033 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
amdgpu_dce_v8_0.c 3123 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h 7293 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
dce_8_0_sh_mask.h 4661 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
dce_10_0_sh_mask.h 5195 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
    [all...]
dce_11_0_sh_mask.h 5307 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
    [all...]
dce_11_2_sh_mask.h 6387 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
    [all...]

Completed in 317 milliseconds