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    Searched refs:HDMI_ACR_32_1 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 80 SRI(HDMI_ACR_32_1, DIG, id),\
184 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
683 uint32_t HDMI_ACR_32_1;
amdgpu_dce_stream_encoder.c 1409 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
rv770d.h 791 #define HDMI_ACR_32_1 0x74b0
evergreend.h 645 #define HDMI_ACR_32_1 0x70e0
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 70 SRI(HDMI_ACR_32_1, DIG, id),\
154 uint32_t HDMI_ACR_32_1;
amdgpu_dcn10_stream_encoder.c 1341 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1501 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
amdgpu_dce_v11_0.c 1543 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
amdgpu_dce_v6_0.c 1432 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);

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