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    Searched refs:HDMI_ACR_44_1 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 82 SRI(HDMI_ACR_44_1, DIG, id),\
186 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
685 uint32_t HDMI_ACR_44_1;
amdgpu_dce_stream_encoder.c 1415 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
rv770d.h 795 #define HDMI_ACR_44_1 0x74b8
evergreend.h 649 #define HDMI_ACR_44_1 0x70e8
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 72 SRI(HDMI_ACR_44_1, DIG, id),\
156 uint32_t HDMI_ACR_44_1;
amdgpu_dcn10_stream_encoder.c 1347 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1508 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
amdgpu_dce_v11_0.c 1550 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
amdgpu_dce_v6_0.c 1439 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);

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