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    Searched refs:HDMI_ACR_48_1 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 84 SRI(HDMI_ACR_48_1, DIG, id),\
188 SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
687 uint32_t HDMI_ACR_48_1;
amdgpu_dce_stream_encoder.c 1421 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
rv770d.h 799 #define HDMI_ACR_48_1 0x74c0
evergreend.h 653 #define HDMI_ACR_48_1 0x70f0
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 74 SRI(HDMI_ACR_48_1, DIG, id),\
158 uint32_t HDMI_ACR_48_1;
amdgpu_dcn10_stream_encoder.c 1353 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1515 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
amdgpu_dce_v11_0.c 1557 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
amdgpu_dce_v6_0.c 1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);

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