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    Searched refs:HDMI_ACR_CTS_32 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 183 SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
263 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
459 uint8_t HDMI_ACR_CTS_32;
590 uint32_t HDMI_ACR_CTS_32;
amdgpu_dce_stream_encoder.c 1406 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
rv770d.h 790 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
evergreend.h 644 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 233 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
423 type HDMI_ACR_CTS_32;\
amdgpu_dcn10_stream_encoder.c 1338 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1498 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
amdgpu_dce_v11_0.c 1540 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
amdgpu_dce_v6_0.c 1429 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);

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