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    Searched refs:HDMI_ACR_CTS_48 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 187 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
267 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
463 uint8_t HDMI_ACR_CTS_48;
594 uint32_t HDMI_ACR_CTS_48;
amdgpu_dce_stream_encoder.c 1418 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
rv770d.h 798 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
evergreend.h 652 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 237 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
427 type HDMI_ACR_CTS_48;\
amdgpu_dcn10_stream_encoder.c 1350 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
amdgpu_dce_v11_0.c 1554 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
amdgpu_dce_v6_0.c 1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);

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