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    Searched refs:HDMI_ACR_PACKET_CONTROL (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 78 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
180 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
181 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
182 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
681 uint32_t HDMI_ACR_PACKET_CONTROL;
amdgpu_dce_stream_encoder.c 1388 /* HDMI_ACR_PACKET_CONTROL */
1389 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
88 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
rv770d.h 695 #define HDMI_ACR_PACKET_CONTROL 0x740c
evergreend.h 540 #define HDMI_ACR_PACKET_CONTROL 0x703c
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 68 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
152 uint32_t HDMI_ACR_PACKET_CONTROL;
amdgpu_dcn10_stream_encoder.c 1320 /* HDMI_ACR_PACKET_CONTROL */
1321 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1679 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1682 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
amdgpu_dce_v11_0.c 1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1726 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
amdgpu_dce_v6_0.c 1423 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1424 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,

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