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    Searched refs:HDMI_ACR_SOURCE (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 181 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
261 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
457 uint8_t HDMI_ACR_SOURCE;
588 uint32_t HDMI_ACR_SOURCE;
amdgpu_dce_stream_encoder.c 1391 HDMI_ACR_SOURCE, 0,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 89 HDMI_ACR_SOURCE | /* select SW CTS value */
rv770d.h 703 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
evergreend.h 548 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 231 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
421 type HDMI_ACR_SOURCE;\
amdgpu_dcn10_stream_encoder.c 1323 HDMI_ACR_SOURCE, 0,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1679 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1682 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
amdgpu_dce_v11_0.c 1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
amdgpu_dce_v6_0.c 1424 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2068 typedef enum HDMI_ACR_SOURCE {
2071 } HDMI_ACR_SOURCE;
dce_11_2_enum.h 2531 typedef enum HDMI_ACR_SOURCE {
2534 } HDMI_ACR_SOURCE;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 6382 * HDMI_ACR_SOURCE enum
6385 typedef enum HDMI_ACR_SOURCE {
6388 } HDMI_ACR_SOURCE;
vega10_enum.h 3913 * HDMI_ACR_SOURCE enum
3916 typedef enum HDMI_ACR_SOURCE {
3919 } HDMI_ACR_SOURCE;

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