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    Searched refs:HDMI_AVI_INFO_CONT (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 421 HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */
429 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
rv770d.h 711 # define HDMI_AVI_INFO_CONT (1 << 1)
evergreend.h 561 # define HDMI_AVI_INFO_CONT (1 << 1)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 752 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
775 HDMI_AVI_INFO_CONT, 1);
783 HDMI_AVI_INFO_CONT, 0);
787 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
dce_stream_encoder.h 154 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
327 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
428 uint8_t HDMI_AVI_INFO_CONT;
559 uint32_t HDMI_AVI_INFO_CONT;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v6_0.c 1595 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1610 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
amdgpu_dce_v10_0.c 1733 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
amdgpu_dce_v11_0.c 1775 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2110 typedef enum HDMI_AVI_INFO_CONT {
2113 } HDMI_AVI_INFO_CONT;
dce_11_2_enum.h 2573 typedef enum HDMI_AVI_INFO_CONT {
2576 } HDMI_AVI_INFO_CONT;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
vega10_enum.h 4000 * HDMI_AVI_INFO_CONT enum
4003 typedef enum HDMI_AVI_INFO_CONT {
4006 } HDMI_AVI_INFO_CONT;

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