HomeSort by: relevance | last modified time | path
    Searched refs:HDMI_CONTROL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 581 REG_UPDATE_3(HDMI_CONTROL,
586 REG_UPDATE_5(HDMI_CONTROL,
596 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
600 REG_UPDATE_2(HDMI_CONTROL,
604 REG_UPDATE_2(HDMI_CONTROL,
611 REG_UPDATE_2(HDMI_CONTROL,
615 REG_UPDATE_2(HDMI_CONTROL,
621 REG_UPDATE_2(HDMI_CONTROL,
635 REG_UPDATE_2(HDMI_CONTROL,
647 REG_UPDATE_2(HDMI_CONTROL,
    [all...]
dce_stream_encoder.h 70 SRI(HDMI_CONTROL, DIG, id), \
138 SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
139 SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
140 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
141 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
304 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
305 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
314 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
315 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
671 uint32_t HDMI_CONTROL;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 518 REG_UPDATE_6(HDMI_CONTROL,
529 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
533 REG_UPDATE_2(HDMI_CONTROL,
537 REG_UPDATE_2(HDMI_CONTROL,
544 REG_UPDATE_2(HDMI_CONTROL,
548 REG_UPDATE_2(HDMI_CONTROL,
554 REG_UPDATE_2(HDMI_CONTROL,
567 REG_UPDATE_2(HDMI_CONTROL,
579 REG_UPDATE_2(HDMI_CONTROL,
1015 REG_UPDATE_5(HDMI_CONTROL,
    [all...]
dcn10_stream_encoder.h 57 SRI(HDMI_CONTROL, DIG, id), \
140 uint32_t HDMI_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 329 val = RREG32(HDMI_CONTROL + offset);
356 WREG32(HDMI_CONTROL + offset, val);
rv770d.h 683 #define HDMI_CONTROL 0x7400
evergreend.h 522 #define HDMI_CONTROL 0x7030
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1632 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
amdgpu_dce_v11_0.c 1661 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1662 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1667 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1668 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1673 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1674 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);

Completed in 27 milliseconds