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    Searched refs:HDMI_GC_CONT (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 142 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
229 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
415 uint8_t HDMI_GC_CONT;
546 uint32_t HDMI_GC_CONT;
amdgpu_dce_stream_encoder.c 654 HDMI_GC_CONT, 1,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 319 HDMI_GC_CONT); /* send general control packets every frame */
rv770d.h 708 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
evergreend.h 558 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 195 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
377 type HDMI_GC_CONT;\
amdgpu_dcn10_stream_encoder.c 586 HDMI_GC_CONT, 1,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_11_0_enum.h 2094 typedef enum HDMI_GC_CONT {
2097 } HDMI_GC_CONT;
dce_11_2_enum.h 2557 typedef enum HDMI_GC_CONT {
2560 } HDMI_GC_CONT;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1642 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
amdgpu_dce_v11_0.c 1684 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
amdgpu_dce_v6_0.c 1408 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 6433 * HDMI_GC_CONT enum
6436 typedef enum HDMI_GC_CONT {
6439 } HDMI_GC_CONT;
vega10_enum.h 3964 * HDMI_GC_CONT enum
3967 typedef enum HDMI_GC_CONT {
3970 } HDMI_GC_CONT;

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