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    Searched refs:HDMI_INFOFRAME_CONTROL1 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 75 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
147 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
155 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
678 uint32_t HDMI_INFOFRAME_CONTROL1;
amdgpu_dce_stream_encoder.c 663 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
777 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 227 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
rv770d.h 716 #define HDMI_INFOFRAME_CONTROL1 0x7418
evergreend.h 566 #define HDMI_INFOFRAME_CONTROL1 0x7048
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_stream_encoder.h 65 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
149 uint32_t HDMI_INFOFRAME_CONTROL1;
amdgpu_dcn10_stream_encoder.c 595 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1659 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1737 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
amdgpu_dce_v11_0.c 1701 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1779 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
amdgpu_dce_v6_0.c 1488 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1601 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

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