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    Searched refs:HDMI_WRITE (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/sunxi/
sunxi_hdmi.c 102 #define HDMI_WRITE(sc, reg, val) \
250 HDMI_WRITE(sc, j, 0);
342 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
348 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val);
352 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val);
354 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len);
356 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type);
360 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
391 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val);
397 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val)
    [all...]
  /src/sys/arch/arm/nvidia/
tegra_drm_mode.c 933 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);
934 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);
935 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,
937 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG,
939 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,
941 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,
945 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG,
963 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst);
964 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst);
970 HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl)
    [all...]
tegra_drm.h 145 #define HDMI_WRITE(enc, reg, val) \
  /src/sys/arch/arm/amlogic/
meson_genfb.c 159 #define HDMI_WRITE meson_genfb_hdmi_write_4

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