| /src/external/gpl3/gdb.old/dist/sim/common/ |
| sim-endian.h | 378 #define U8_1(I0,I1,I2,I3,I4,I5,I6,I7) \
380 | V8_1(I4,4) | V8_1(I5,5) | V8_1(I6,6) | V8_1(I7,7))
381 #define U16_1(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15) \
383 | V16_1(I4,4) | V16_1(I5,5) | V16_1(I6,6) | V16_1(I7,7) \
389 #define U16_2(I0,I1,I2,I3,I4,I5,I6,I7) \
391 | V16_2(I4,4) | V16_2(I5,5) | V16_2(I6,6) | V16_2(I7,7) )
|
| /src/external/gpl3/gdb/dist/sim/common/ |
| sim-endian.h | 378 #define U8_1(I0,I1,I2,I3,I4,I5,I6,I7) \
380 | V8_1(I4,4) | V8_1(I5,5) | V8_1(I6,6) | V8_1(I7,7))
381 #define U16_1(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15) \
383 | V16_1(I4,4) | V16_1(I5,5) | V16_1(I6,6) | V16_1(I7,7) \
389 #define U16_2(I0,I1,I2,I3,I4,I5,I6,I7) \
391 | V16_2(I4,4) | V16_2(I5,5) | V16_2(I6,6) | V16_2(I7,7) )
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 164 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
302 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
328 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
354 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
|
| DelaySlotFiller.cpp | 384 if (reg < SP::I0 || reg > SP::I7)
412 if (reg < SP::I0 || reg > SP::I7)
450 if (reg < SP::I0 || reg > SP::I7)
|
| SparcRegisterInfo.cpp | 72 Reserved.set(SP::I7);
|
| /src/external/bsd/pcc/dist/pcc/arch/sparc64/ |
| macdefs.h | 151 #define I7 30
258 #define GCLASS(x) (x <= I7 ? CLASSA : \
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| mcore-opc.h | 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
153 { "movi", I7, 0, 0x6000 },
|
| mcore-dis.c | 43 /* I7 */ 0xF800,
191 case I7:
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| mcore-opc.h | 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
153 { "movi", I7, 0, 0x6000 },
|
| mcore-dis.c | 43 /* I7 */ 0xF800,
188 case I7:
|
| /src/external/gpl3/gcc/dist/libgcc/soft-fp/ |
| op-8.h | 231 #define __FP_FRAC_SET_8(X, I7, I6, I5, I4, I3, I2, I1, I0) \
232 (X##_f[7] = I7, X##_f[6] = I6, X##_f[5] = I5, X##_f[4] = I4, \
|
| /src/external/gpl3/gcc.old/dist/libgcc/soft-fp/ |
| op-8.h | 234 #define __FP_FRAC_SET_8(X, I7, I6, I5, I4, I3, I2, I1, I0) \
235 (X##_f[7] = I7, X##_f[6] = I6, X##_f[5] = I5, X##_f[4] = I4, \
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| mcore-opc.h | 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
153 { "movi", I7, 0, 0x6000 },
|
| mcore-dis.c | 43 /* I7 */ 0xF800,
188 case I7:
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| mcore-opc.h | 26 OMa, SI, I7, LS, BR, BL, LR, LJ,
153 { "movi", I7, 0, 0x6000 },
|
| mcore-dis.c | 43 /* I7 */ 0xF800,
188 case I7:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcInstPrinter.cpp | 73 case SP::I7: O << "\tret"; return true;
|
| /src/external/gpl3/gdb/dist/gdb/stubs/ |
| sparc-stub.c | 113 I0, I1, I2, I3, I4, I5, FP, I7,
|
| /src/external/gpl3/gdb.old/dist/gdb/stubs/ |
| sparc-stub.c | 113 I0, I1, I2, I3, I4, I5, FP, I7,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 143 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
467 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 68 SP::I4, SP::I5, SP::I6, SP::I7 };
|
| /src/external/gpl3/binutils/dist/zlib/contrib/masmx64/ |
| gvmat64.asm | 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
|
| /src/external/gpl3/binutils.old/dist/zlib/contrib/masmx64/ |
| gvmat64.asm | 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
|
| /src/external/gpl3/gdb/dist/zlib/contrib/masmx64/ |
| gvmat64.asm | 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
|
| /src/external/gpl3/gdb.old/dist/zlib/contrib/masmx64/ |
| gvmat64.asm | 7 ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
|
