| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_suspend.c | 80 I915_WRITE(reg + (i << 2), array[i]);
383 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
388 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
392 I915_WRITE(FPA0, dev_priv->saveFPA0);
393 I915_WRITE(FPA1, dev_priv->saveFPA1);
395 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
398 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
402 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
403 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
404 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A)
[all...] |
| i915_irq.c | 61 I915_WRITE(IMR, dev_priv->irq_mask_reg);
72 I915_WRITE(IMR, dev_priv->irq_mask_reg);
95 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
107 I915_WRITE(reg, dev_priv->pipestat[pipe]);
204 I915_WRITE(PIPEASTAT, pipea_stats);
211 I915_WRITE(PIPEBSTAT, pipeb_stats);
215 I915_WRITE(IIR, iir);
475 I915_WRITE(HWSTAM, 0xeffe);
476 I915_WRITE(PIPEASTAT, 0);
477 I915_WRITE(PIPEBSTAT, 0)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_vdsc.c | 528 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
534 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
536 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
538 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
547 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
553 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
555 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
557 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
567 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
573 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val)
[all...] |
| vlv_dsi.c | 108 I915_WRITE(reg, val);
169 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
177 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
231 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
237 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
337 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
343 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
352 I915_WRITE(MIPI_CTRL(port), tmp);
387 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
395 I915_WRITE(MIPI_DEVICE_READY(port), val)
[all...] |
| intel_combo_phy.c | 92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
94 I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
95 I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
161 I915_WRITE(CHICKEN_MISC_2, val);
168 I915_WRITE(CNL_PORT_COMP_DW0, val);
172 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
184 I915_WRITE(CHICKEN_MISC_2, val);
268 I915_WRITE(ICL_PORT_CL_DW10(phy), val);
330 I915_WRITE(ICL_PHY_MISC(phy), val);
338 I915_WRITE(ICL_PORT_COMP_DW8(phy), val)
[all...] |
| intel_color.c | 165 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
166 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
167 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
169 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
170 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
172 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
173 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
175 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
176 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
179 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0])
[all...] |
| icl_dsi.c | 144 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
183 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
225 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
232 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
240 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
248 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
256 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
266 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
301 I915_WRITE(DSS_CTL2, dss_ctl2);
307 I915_WRITE(DSS_CTL1, dss_ctl1)
[all...] |
| intel_fbc.c | 112 I915_WRITE(FBC_CONTROL, fbc_ctl);
142 I915_WRITE(FBC_TAG(i), 0);
152 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
153 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
165 I915_WRITE(FBC_CONTROL, fbc_ctl);
186 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
188 I915_WRITE(DPFC_FENCE_YOFF, 0);
192 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
203 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
215 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE)
[all...] |
| intel_audio.c | 307 I915_WRITE(reg_elda, tmp);
334 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
365 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
370 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
374 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
408 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
421 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
454 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
463 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
497 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp)
[all...] |
| intel_ddi.c | 993 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
995 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
1027 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1029 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1132 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1146 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1150 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1157 I915_WRITE(DP_TP_CTL(PORT_E),
1167 I915_WRITE(DDI_BUF_CTL(PORT_E)
[all...] |
| vlv_dsi_pll.c | 248 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
353 I915_WRITE(MIPI_CTRL(port), temp |
401 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
402 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
456 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
518 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
532 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
557 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
561 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
565 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp)
[all...] |
| intel_dsb.c | 67 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
87 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
208 I915_WRITE(reg, val);
282 I915_WRITE(reg, val);
323 I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
336 I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
|
| intel_tv.c | 934 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
945 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
1388 I915_WRITE(TV_H_CTL_1, hctl1);
1389 I915_WRITE(TV_H_CTL_2, hctl2);
1390 I915_WRITE(TV_H_CTL_3, hctl3);
1391 I915_WRITE(TV_V_CTL_1, vctl1);
1392 I915_WRITE(TV_V_CTL_2, vctl2);
1393 I915_WRITE(TV_V_CTL_3, vctl3);
1394 I915_WRITE(TV_V_CTL_4, vctl4);
1395 I915_WRITE(TV_V_CTL_5, vctl5)
[all...] |
| intel_panel.c | 620 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
630 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
658 I915_WRITE(BLC_PWM_CTL, tmp | level);
669 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
678 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
763 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
767 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
779 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
782 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
798 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE)
[all...] |
| intel_fifo_underrun.c | 107 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
126 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
158 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
171 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
224 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
239 I915_WRITE(SERR_INT,
|
| intel_hdcp.c | 194 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
195 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
232 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
245 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
253 I915_WRITE(HDCP_SHA_TEXT, sha_text);
321 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
338 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
355 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
387 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
395 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0)
[all...] |
| intel_dpll_mgr.c | 403 I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
404 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
428 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
439 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
449 I915_WRITE(PCH_DPLL(id), 0);
514 I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
522 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
534 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
552 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
1006 I915_WRITE(DPLL_CTRL1, val)
[all...] |
| intel_dpio_phy.c | 288 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
293 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
303 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
308 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
312 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
383 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
404 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
409 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
415 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
420 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val)
[all...] |
| intel_dvo.c | 201 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
218 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
306 /*I915_WRITE(DVOB_SRCDIM,
309 I915_WRITE(dvo_srcdim_reg,
312 /*I915_WRITE(DVOB, dvo_val);*/
313 I915_WRITE(dvo_reg, dvo_val);
490 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
497 I915_WRITE(DPLL(pipe), dpll[pipe]);
|
| intel_hdmi.c | 233 I915_WRITE(VIDEO_DIP_CTL, val);
236 I915_WRITE(VIDEO_DIP_DATA, *data);
241 I915_WRITE(VIDEO_DIP_DATA, 0);
247 I915_WRITE(VIDEO_DIP_CTL, val);
265 I915_WRITE(VIDEO_DIP_CTL, val);
306 I915_WRITE(reg, val);
309 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
314 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
320 I915_WRITE(reg, val);
339 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val)
[all...] |
| intel_cdclk.c | 518 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
521 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
744 I915_WRITE(LCPLL_CTL, val);
775 I915_WRITE(LCPLL_CTL, val);
779 I915_WRITE(LCPLL_CTL, val);
788 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
973 I915_WRITE(DPLL_CTRL1, val);
976 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
989 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
1058 I915_WRITE(CDCLK_CTL, cdclk_ctl)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_suspend.c | 57 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
64 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
122 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
126 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
131 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
132 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
135 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
141 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i])
[all...] |
| intel_pm.c | 68 I915_WRITE(CHICKEN_PAR1_1,
74 I915_WRITE(CHICKEN_PAR1_1,
78 I915_WRITE(GEN8_CHICKEN_DCPR_1,
83 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
88 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
93 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
103 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
110 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
117 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
126 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950))
[all...] |
| i915_irq.c | 275 I915_WRITE(PORT_HOTPLUG_EN, val);
324 I915_WRITE(DEIMR, dev_priv->irq_mask);
356 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
388 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
414 I915_WRITE(SDEIMR, sdeimr);
478 I915_WRITE(reg, enable_mask | status_mask);
501 I915_WRITE(reg, enable_mask | status_mask);
932 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
951 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
977 I915_WRITE(GEN7_MISCCPCTL, misccpctl)
[all...] |
| i915_drv.c | 1370 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
2333 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2334 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2335 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2336 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2337 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2340 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2342 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2343 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2345 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp)
[all...] |
