Searched refs:JH7110_STGCLK_PCIE_SLV_MAIN (Results 1 - 2 of 2) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h243 #define JH7110_STGCLK_PCIE_SLV_MAIN 14 macro
/src/sys/arch/riscv/starfive/
H A Djh7110_clkc.c279 #define JH7110_STGCLK_PCIE_SLV_MAIN 14 macro
722 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", "stg_axiahb"), // CLK_IS_CRITICAL

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