Searched refs:JH7110_SYSCLK_DDR_BUS (Results 1 - 2 of 2) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h60 #define JH7110_SYSCLK_DDR_BUS 43 macro
/src/sys/arch/riscv/starfive/
H A Djh7110_clkc.c91 #define JH7110_SYSCLK_DDR_BUS 43 macro
475 JH71X0CLKC_MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", ddr_bus_parents),

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