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    Searched refs:LVDS (Results 1 - 19 of 19) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7.h 182 LVDS,
smu71.h 474 LVDS,
smu72.h 554 LVDS,
smu73.h 545 LVDS,
smu74.h 608 LVDS,
smu75.h 502 LVDS,
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/
nouveau_nvkm_engine_disp_sornv50.c 80 case 0: state->proto = LVDS; state->link = 1; break;
nouveau_nvkm_engine_disp_sorgv100.c 71 case 0: state->proto = LVDS; state->link = 1; break;
ior.h 31 LVDS,
nouveau_nvkm_engine_disp_sorgf119.c 149 case 0: state->proto = LVDS; state->link = 1; break;
nouveau_nvkm_engine_disp_outp.c 72 case DCB_OUTPUT_LVDS : *type = SOR; return LVDS;
nouveau_nvkm_engine_disp_sorg94.c 250 case 0: state->proto = LVDS; state->link = 1; break;
nouveau_nvkm_engine_disp_nv50.c 225 if (ior->asy.proto == LVDS) {
450 * A) Give dual-link LVDS a separate EVO protocol, like for TMDS.
452 * B) Use SetControlOutputResource.PixelDepth on LVDS.
457 if (ior->type == SOR && ior->asy.proto == LVDS) {
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7.h 163 LVDS,
  /src/sys/external/bsd/drm/dist/shared-core/
i915_suspend.c 314 /* LVDS state */
321 dev_priv->saveLVDS = I915_READ(LVDS);
473 /* LVDS state */
477 I915_WRITE(LVDS, dev_priv->saveLVDS);
i915_reg.h 377 #define LVDS 0x61180
409 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
674 /* LVDS port control */
675 #define LVDS 0x61180
677 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
678 * the DPLL semantics change when the LVDS is assigned to that pipe.
681 /* Selects pipe B for LVDS data. Must be set on pre-965. */
722 * - LVDS/DVOB/DVOC on
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_lvds.c 55 /* Private structure for the integrated LVDS support */
200 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
287 * Set the dithering flag on LVDS as needed, note that there is no
288 * special lvds dither control bit on pch-split platforms, dithering is
293 * Bspec wording suggests that LVDS port dithering only exists
406 DRM_ERROR("Can't support LVDS on pipe A\n");
416 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
506 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
510 /* These systems claim to have LVDS, but really don't */
725 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident)
829 u32 lvds; local
    [all...]
intel_display.c 454 /* LVDS 100mhz refclk limits. */
686 * For LVDS just rely on its current settings for dual-channel.
710 * divider from @match_clock used for LVDS downclocking.
768 * divider from @match_clock used for LVDS downclocking.
824 * divider from @match_clock used for LVDS downclocking.
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
5795 * the right LVDS enable sequence. */
7919 * - LVDS dual channel mode
7930 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n")
11945 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 3422 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
4750 /* LVDS port control */
4751 #define LVDS _MMIO(0x61180)
4753 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4754 * the DPLL semantics change when the LVDS is assigned to that pipe.
4757 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4764 /* LVDS dithering flag on 965/g4x platform */
4766 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4875 * - LVDS/DVOB/DVOC on

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