1 /* $NetBSD: smu7.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU7_H 27 #define SMU7_H 28 29 #pragma pack(push, 1) 30 31 #define SMU7_CONTEXT_ID_SMC 1 32 #define SMU7_CONTEXT_ID_VBIOS 2 33 34 35 #define SMU7_CONTEXT_ID_SMC 1 36 #define SMU7_CONTEXT_ID_VBIOS 2 37 38 #define SMU7_MAX_LEVELS_VDDC 8 39 #define SMU7_MAX_LEVELS_VDDCI 4 40 #define SMU7_MAX_LEVELS_MVDD 4 41 #define SMU7_MAX_LEVELS_VDDNB 8 42 43 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 44 #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 45 #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 46 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 47 #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 48 #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 49 #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 50 #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 51 #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 52 53 #define DPM_NO_LIMIT 0 54 #define DPM_NO_UP 1 55 #define DPM_GO_DOWN 2 56 #define DPM_GO_UP 3 57 58 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 59 #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 60 61 #define GPIO_CLAMP_MODE_VRHOT 1 62 #define GPIO_CLAMP_MODE_THERM 2 63 #define GPIO_CLAMP_MODE_DC 4 64 65 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 66 #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 67 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 68 #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 69 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 70 #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 71 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 72 #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 73 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 74 #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 75 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 76 #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 77 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 78 #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 79 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 80 #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 81 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 82 #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 83 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 84 #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 85 86 87 struct SMU7_PIDController 88 { 89 uint32_t Ki; 90 int32_t LFWindupUL; 91 int32_t LFWindupLL; 92 uint32_t StatePrecision; 93 uint32_t LfPrecision; 94 uint32_t LfOffset; 95 uint32_t MaxState; 96 uint32_t MaxLfFraction; 97 uint32_t StateShift; 98 }; 99 100 typedef struct SMU7_PIDController SMU7_PIDController; 101 102 // ------------------------------------------------------------------------------------------------------------------------- 103 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 104 105 #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 106 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 107 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 108 #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 109 #define SMU7_UVD_DPM_CONFIG_MASK 0x10 110 #define SMU7_VCE_DPM_CONFIG_MASK 0x20 111 #define SMU7_ACP_DPM_CONFIG_MASK 0x40 112 #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 113 #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 114 115 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 116 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 117 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 118 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 119 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 120 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 121 122 struct SMU7_Firmware_Header 123 { 124 uint32_t Digest[5]; 125 uint32_t Version; 126 uint32_t HeaderSize; 127 uint32_t Flags; 128 uint32_t EntryPoint; 129 uint32_t CodeSize; 130 uint32_t ImageSize; 131 132 uint32_t Rtos; 133 uint32_t SoftRegisters; 134 uint32_t DpmTable; 135 uint32_t FanTable; 136 uint32_t CacConfigTable; 137 uint32_t CacStatusTable; 138 139 uint32_t mcRegisterTable; 140 141 uint32_t mcArbDramTimingTable; 142 143 uint32_t PmFuseTable; 144 uint32_t Globals; 145 uint32_t Reserved[42]; 146 uint32_t Signature; 147 }; 148 149 typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 150 151 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 152 153 enum DisplayConfig { 154 PowerDown = 1, 155 DP54x4, 156 DP54x2, 157 DP54x1, 158 DP27x4, 159 DP27x2, 160 DP27x1, 161 HDMI297, 162 HDMI162, 163 LVDS, 164 DP324x4, 165 DP324x2, 166 DP324x1 167 }; 168 169 #pragma pack(pop) 170 171 #endif 172 173
Indexes created Sat Sep 20 22:09:52 GMT 2025