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    Searched refs:MAX_PIPES (Results 1 - 23 of 23) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 161 struct mem_input *mis[MAX_PIPES];
162 struct hubp *hubps[MAX_PIPES];
163 struct input_pixel_processor *ipps[MAX_PIPES];
164 struct transform *transforms[MAX_PIPES];
165 struct dpp *dpps[MAX_PIPES];
166 struct output_pixel_processor *opps[MAX_PIPES];
167 struct timing_generator *timing_generators[MAX_PIPES];
168 struct stream_encoder *stream_enc[MAX_PIPES * 2];
172 struct dce_aux *engines[MAX_PIPES];
173 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
opp.h 202 int dpp[MAX_PIPES];
203 int mpcc[MAX_PIPES];
211 bool mpcc_disconnect_pending[MAX_PIPES];
hw_shared.h 40 #define MAX_PIPES 6
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_stream.c 298 for (i = 0; i < MAX_PIPES; i++) {
345 for (i = 0; i < MAX_PIPES; i++) {
515 for (i = 0; i < MAX_PIPES; i++) {
543 for (i = 0; i < MAX_PIPES; i++) {
574 for (i = 0; i < MAX_PIPES; i++) {
601 for (i = 0; i < MAX_PIPES; i++) {
607 if (i == MAX_PIPES)
629 for (i = 0; i < MAX_PIPES; i++) {
635 if (i == MAX_PIPES)
amdgpu_dc.c 291 for (i = 0; i < MAX_PIPES; i++) {
318 for (i = 0; i < MAX_PIPES; i++) {
352 for (i = 0; i < MAX_PIPES; i++) {
358 if (i == MAX_PIPES)
401 for (i = 0; i < MAX_PIPES; i++) {
407 if (i == MAX_PIPES)
425 for (i = 0; i < MAX_PIPES; i++) {
447 for (i = 0; i < MAX_PIPES; i++) {
484 for (i = 0; i < MAX_PIPES; i++) {
501 for (i = 0; i < MAX_PIPES; i++)
    [all...]
amdgpu_dc_debug.c 317 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
amdgpu_dc_link_hwss.c 115 for (i = 0; i < MAX_PIPES; i++) {
319 for (i = 0; i < MAX_PIPES; i++) {
amdgpu_dc_link.c 2357 for (i = 0; i < MAX_PIPES; i++) {
2523 for (i = 0; i < MAX_PIPES; i++) {
2881 for (i = 0; i < MAX_PIPES; i++) {
2899 for (i = 0; i < MAX_PIPES; i++) {
3296 for (i = 0; i < MAX_PIPES; i++) {
3307 if (i == MAX_PIPES)
amdgpu_dc_resource.c 457 for (i = 0; i < MAX_PIPES; i++) {
1088 for (i = 0; i < MAX_PIPES; i++) {
1164 for (i = 0; i < MAX_PIPES; i++) {
2509 for (i = 0; i < MAX_PIPES; i++) {
amdgpu_dc_link_dp.c 2893 for (i = 0; i < MAX_PIPES; i++) {
3805 for (i = 0; i < MAX_PIPES; i++) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clock_source.h 154 uint32_t PHASE[MAX_PIPES];
155 uint32_t MODULO[MAX_PIPES];
156 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
dmub_psr.c 39 #define MAX_PIPES 6
110 for (int i = 0; i < MAX_PIPES; i++) {
dce_clk_mgr.c 194 for (i = 0; i < MAX_PIPES; i++) {
511 for (k = 0; k < MAX_PIPES; k++)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_mst_types.c 590 bool bpp_increased[MAX_PIPES];
591 int initial_slack[MAX_PIPES];
687 bool tried[MAX_PIPES];
688 int kbps_increase[MAX_PIPES];
751 struct dsc_mst_fairness_params params[MAX_PIPES];
752 struct dsc_mst_fairness_vars vars[MAX_PIPES];
845 bool computed_streams[MAX_PIPES];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 139 for (k = 0; k < MAX_PIPES; k++)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
amdgpu_dce_clk_mgr.c 175 for (i = 0; i < MAX_PIPES; i++) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc.h 498 struct dc_link *links[MAX_PIPES * 2];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 966 for (i = 0; i < MAX_PIPES; i++) {
1642 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1683 for (i = 0; i < MAX_PIPES; i++) {
1878 for (i = 0; i < MAX_PIPES; i++) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 618 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
918 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
1562 bool pipe_locked[MAX_PIPES] = {false};
2346 for (j = 0; j < MAX_PIPES; j++)
amdgpu_dcn20_resource.c 1620 for (i = 0; i < MAX_PIPES; i++) {
2555 bool split[MAX_PIPES] = { false };
2581 for (i = 0; i < MAX_PIPES; i++)
2782 bool visited[MAX_PIPES] = { 0 };
2887 int pipe_split_from[MAX_PIPES];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 1137 int pipe_split_from[MAX_PIPES];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 2862 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dce_calcs.c 2989 const struct pipe_ctx *active_pipes[MAX_PIPES];

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