| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v10.c | 61 * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
65 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
66 MC_ARB_RAMCFG, NOOFBANK);
67 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
68 MC_ARB_RAMCFG, NOOFRANKS);
|
| amdgpu_amdkfd_gfx_v7.c | 101 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
102 MC_ARB_RAMCFG, NOOFBANK);
103 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
104 MC_ARB_RAMCFG, NOOFRANKS);
|
| amdgpu_amdkfd_gfx_v8.c | 58 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
59 MC_ARB_RAMCFG, NOOFBANK);
60 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
61 MC_ARB_RAMCFG, NOOFRANKS);
|
| amdgpu_gmc_v7_0.c | 338 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
|
| amdgpu_gmc_v8_0.c | 540 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
|
| amdgpu_si.c | 997 {MC_ARB_RAMCFG},
1070 return adev->gfx.config.mc_arb_ramcfg;
|
| sid.h | 501 #define MC_ARB_RAMCFG 0x9D8
|
| amdgpu_si_dpm.c | 3683 tmp = RREG32(MC_ARB_RAMCFG);
4749 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
|
| amdgpu_gfx_v8_0.c | 1688 u32 mc_arb_ramcfg; local
1828 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1829 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1860 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv770d.h | 445 #define MC_ARB_RAMCFG 0x2760
|
| radeon_rv770.c | 1192 u32 mc_arb_ramcfg; local
1308 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1364 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1370 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1371 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1376 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1378 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1657 tmp = RREG32(MC_ARB_RAMCFG);
|
| nid.h | 192 #define MC_ARB_RAMCFG 0x2760
|
| cikd.h | 625 #define MC_ARB_RAMCFG 0x2760
|
| sid.h | 499 #define MC_ARB_RAMCFG 0x2760
|
| evergreend.h | 933 #define MC_ARB_RAMCFG 0x2760
|
| radeon_ni.c | 901 u32 mc_shared_chmap __unused, mc_arb_ramcfg; local
1027 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1029 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1080 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
|
| radeon_rv770_dpm.c | 734 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
|
| radeon_evergreen.c | 3141 u32 mc_shared_chmap __unused, mc_arb_ramcfg; local
3409 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
3411 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3440 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3727 tmp = RREG32(MC_ARB_RAMCFG);
|
| radeon_si.c | 3103 u32 mc_shared_chmap __unused, mc_arb_ramcfg; local
3216 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3220 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3268 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
4220 tmp = RREG32(MC_ARB_RAMCFG);
|
| radeon_cik.c | 3198 u32 mc_shared_chmap __unused, mc_arb_ramcfg; local
3292 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3296 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3345 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
5362 tmp = RREG32(MC_ARB_RAMCFG);
|
| radeon_si_dpm.c | 3223 tmp = RREG32(MC_ARB_RAMCFG);
4283 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
|
