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Searched refs:MC_SEQ_MISC0_GDDR5_MASK (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`123 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
nid.h	`213 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 794 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
rv770d.h	`289 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
cikd.h	`686 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
sid.h	`561 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
radeon_ni.c	`678 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;`
radeon_rv770_dpm.c	`1601 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==`
radeon_ci_dpm.c	`5106 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==`
radeon_si_dpm.c	`3216 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`563 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`
amdgpu_si_dpm.c	`3676 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c	`84 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000`

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