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Searched refs:MC_SEQ_RD_CTL_D1_LP (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`161 #define MC_SEQ_RD_CTL_D1_LP 0x2b20`
nid.h	`819 #define MC_SEQ_RD_CTL_D1_LP 0x2b20`
cikd.h	`712 #define MC_SEQ_RD_CTL_D1_LP 0x2b20`
sid.h	`587 #define MC_SEQ_RD_CTL_D1_LP 0x2b20`
radeon_btc_dpm.c	`1881 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 2040 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));`
evergreend.h	`337 #define MC_SEQ_RD_CTL_D1_LP 0x2b20`
radeon_cypress_dpm.c	`997 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;`
radeon_ni_dpm.c	`2793 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 2897 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));`
radeon_ci_dpm.c	`4452 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 4658 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));`
radeon_si_dpm.c	`5450 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5558 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`589 #define MC_SEQ_RD_CTL_D1_LP 0xAC8`
amdgpu_si_dpm.c	`5906 *out_reg = MC_SEQ_RD_CTL_D1_LP; 6014 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));`

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