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Searched refs:MC_SEQ_WR_CTL_D0 (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`113 #define MC_SEQ_WR_CTL_D0 0x28bc`
nid.h	`789 #define MC_SEQ_WR_CTL_D0 0x28bc`
cikd.h	`663 #define MC_SEQ_WR_CTL_D0 0x28bc`
sid.h	`550 #define MC_SEQ_WR_CTL_D0 0x28bc`
radeon_btc_dpm.c	`1883 case MC_SEQ_WR_CTL_D0 >> 2: 2041 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
radeon_ci_dpm.c	`4454 case MC_SEQ_WR_CTL_D0 >> 2: 4566 case MC_SEQ_WR_CTL_D0: 4655 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
evergreend.h	`295 #define MC_SEQ_WR_CTL_D0 0x28bc`
radeon_cypress_dpm.c	`1002 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;`
radeon_ni_dpm.c	`2795 case MC_SEQ_WR_CTL_D0 >> 2: 2894 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
radeon_si_dpm.c	`5452 case MC_SEQ_WR_CTL_D0 >> 2: 5555 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`552 #define MC_SEQ_WR_CTL_D0 0xA2F`
amdgpu_si_dpm.c	`5908 case MC_SEQ_WR_CTL_D0: 6011 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`

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