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Searched refs:MC_SEQ_WR_CTL_D0_LP (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`153 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c`
nid.h	`811 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c`
cikd.h	`704 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c`
sid.h	`579 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c`
radeon_btc_dpm.c	`1884 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 2041 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
evergreend.h	`329 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c`
radeon_cypress_dpm.c	`1001 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;`
radeon_ni_dpm.c	`2796 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 2894 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
radeon_ci_dpm.c	`4455 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 4655 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
radeon_si_dpm.c	`5453 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5555 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`581 #define MC_SEQ_WR_CTL_D0_LP 0xA9F`
amdgpu_si_dpm.c	`5909 *out_reg = MC_SEQ_WR_CTL_D0_LP; 6011 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));`

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