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Searched refs:MC_SEQ_WR_CTL_D1 (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`114 #define MC_SEQ_WR_CTL_D1 0x28c0`
nid.h	`790 #define MC_SEQ_WR_CTL_D1 0x28c0`
cikd.h	`664 #define MC_SEQ_WR_CTL_D1 0x28c0`
sid.h	`551 #define MC_SEQ_WR_CTL_D1 0x28c0`
radeon_btc_dpm.c	`1886 case MC_SEQ_WR_CTL_D1 >> 2: 2042 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
radeon_ci_dpm.c	`4457 case MC_SEQ_WR_CTL_D1 >> 2: 4575 case MC_SEQ_WR_CTL_D1: 4656 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
evergreend.h	`296 #define MC_SEQ_WR_CTL_D1 0x28c0`
radeon_cypress_dpm.c	`1006 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;`
radeon_ni_dpm.c	`2798 case MC_SEQ_WR_CTL_D1 >> 2: 2895 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
radeon_si_dpm.c	`5455 case MC_SEQ_WR_CTL_D1 >> 2: 5556 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`553 #define MC_SEQ_WR_CTL_D1 0xA30`
amdgpu_si_dpm.c	`5911 case MC_SEQ_WR_CTL_D1: 6012 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`

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